anv: add missing data flush out of L3 for transform feedback writes

Fixes zink's piglit.spec.arb_shader_image_load_store.host-mem-barrier on TGL

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28492>
This commit is contained in:
Lionel Landwerlin
2023-11-01 02:13:08 +02:00
committed by Marge Bot
parent f60956d002
commit fe36cf6cad
2 changed files with 1 additions and 4 deletions

View File

@@ -449,10 +449,6 @@ spec@arb_sample_shading@samplemask 8@sample mask_in_one,Fail
spec@arb_shader_image_load_store@early-z,Fail
spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail
spec@arb_shader_image_load_store@host-mem-barrier,Fail
spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/16x16,Fail
spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/4x4,Fail
spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/64x64,Fail
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail

View File

@@ -3604,6 +3604,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
* tile cache flush to make sure any previous write is not going to
* create WaW hazards.
*/
pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_2_SHADER_STORAGE_READ_BIT: