anv: add missing data flush out of L3 for transform feedback writes
Fixes zink's piglit.spec.arb_shader_image_load_store.host-mem-barrier on TGL Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28492>
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@@ -449,10 +449,6 @@ spec@arb_sample_shading@samplemask 8@sample mask_in_one,Fail
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spec@arb_shader_image_load_store@early-z,Fail
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spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail
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spec@arb_shader_image_load_store@host-mem-barrier,Fail
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spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/16x16,Fail
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spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/4x4,Fail
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spec@arb_shader_image_load_store@host-mem-barrier@Transform feedback/WaW/one bit barrier test/64x64,Fail
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spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,Fail
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@@ -3604,6 +3604,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
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* tile cache flush to make sure any previous write is not going to
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* create WaW hazards.
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*/
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pipe_bits |= ANV_PIPE_DATA_CACHE_FLUSH_BIT;
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pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
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break;
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case VK_ACCESS_2_SHADER_STORAGE_READ_BIT:
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