nir: change "user_data_amd" sysval from 4 to 8 components
so that we can pass more fast constants to compute shaders (without reading memory in the shader). Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28606>
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@@ -12,6 +12,7 @@ void ac_add_arg(struct ac_shader_args *info, enum ac_arg_regfile regfile, unsign
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enum ac_arg_type type, struct ac_arg *arg)
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{
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assert(info->arg_count < AC_MAX_ARGS);
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assert(nir_num_components_valid(size));
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unsigned offset;
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if (regfile == AC_ARG_SGPR) {
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@@ -1012,7 +1012,7 @@ system_value("color0", 4)
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system_value("color1", 4)
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# System value for internal compute shaders in radeonsi.
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system_value("user_data_amd", 4)
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system_value("user_data_amd", 8)
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# In a fragment shader, the current sample mask. At the beginning of the shader,
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# this is the same as load_sample_mask_in, but as the shader is executed, it may
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@@ -532,7 +532,7 @@ typedef struct shader_info {
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struct {
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uint16_t workgroup_size_hint[3];
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uint8_t user_data_components_amd:3;
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uint8_t user_data_components_amd:4;
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/*
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* Arrangement of invocations used to calculate derivatives in a compute
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@@ -746,7 +746,7 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
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}
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case nir_intrinsic_load_user_data_amd:
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replacement = ac_nir_load_arg(b, &args->ac, args->cs_user_data);
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replacement = nir_pad_vec4(b, replacement);
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replacement = nir_pad_vector(b, replacement, 8);
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break;
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default:
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return false;
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@@ -1159,7 +1159,7 @@ struct si_context {
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unsigned border_color_count;
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unsigned num_vs_blit_sgprs;
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uint32_t vs_blit_sh_data[MAX_SI_VS_BLIT_SGPRS];
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uint32_t cs_user_data[4];
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uint32_t cs_user_data[8];
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/* Vertex buffers. */
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bool vertex_buffers_dirty;
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