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radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export

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We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
This commit is contained in:
Marek Olšák
2022-05-13 22:34:17 -04:00
committed by Marge Bot
parent ba02ed91a6
commit fcaa9f5096
6 changed files with 18 additions and 22 deletions
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2
src/amd/vulkan/radv_pipeline.c
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@@ -6208,7 +6208,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct rade
radeon_set_context_reg(
ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil,
ps->info.ps.writes_sample_mask));
ps->info.ps.writes_sample_mask, false));
}
static void