diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c774cd2b4f3..14d2aeaed41 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -635,6 +635,12 @@ radv_cmd_buffer_annotate(struct radv_cmd_buffer *cmd_buffer, const char *annotat device->ws->cs_annotate(cmd_buffer->cs, annotation); } +#define RADV_TASK_SHADER_SENSITIVE_STAGES (\ + VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT |\ + VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT |\ + VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT |\ + VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT) + static void radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_stage_mask, VkPipelineStageFlags2 dst_stage_mask) @@ -644,8 +650,8 @@ radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_ cmd_buffer->state.flush_bits & RADV_CMD_FLUSH_ALL_COMPUTE & ~RADV_CMD_FLAG_CS_PARTIAL_FLUSH; /* Add stage flush only when necessary. */ - if (src_stage_mask & (VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | - VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_EXT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | + if (src_stage_mask & (VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | VK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_EXT | + VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT | RADV_TASK_SHADER_SENSITIVE_STAGES | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) cmd_buffer->gang.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH; @@ -657,7 +663,7 @@ radv_gang_barrier(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_ /* Increment the GFX/ACE semaphore when task shaders are blocked. */ if (dst_stage_mask & (VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT | VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | - VK_PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT)) + RADV_TASK_SHADER_SENSITIVE_STAGES)) cmd_buffer->gang.sem.leader_value++; }