freedreno/a6xx: enable LRZ by default

Now that dEQP should be happy, lets flip the switch.

Signed-off-by: Rob Clark <robdclark@chromium.org>

src/gallium/drivers/freedreno/a6xx/fd6_resource.c

@@ -323,7 +323,7 @@ fd6_setup_slices(struct fd_resource *rsc)
 {
 	uint32_t alignment;
 
-	if ((fd_mesa_debug & FD_DBG_LRZ) && has_depth(rsc->base.format))
+	if (!(fd_mesa_debug & FD_DBG_NOLRZ) && has_depth(rsc->base.format))
 		setup_lrz(rsc);
 
 	switch (rsc->base.target) {

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -82,13 +82,14 @@ static const struct debug_named_value debug_options[] = {
 		{"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
 		{"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
 		{"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
-		{"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
+		{"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx)"},
 		{"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
 		{"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
 		{"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
 		{"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a3xx/a5xx)"},
 		{"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
 		{"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
+		{"nolrz",     FD_DBG_NOLRZ,  "Disable LRZ (a6xx)"},
 		DEBUG_NAMED_VALUE_END
 };
 

src/gallium/drivers/freedreno/freedreno_util.h

@@ -85,6 +85,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
 #define FD_DBG_TTILE  0x200000
 #define FD_DBG_PERFC  0x400000
 #define FD_DBG_NOUBWC 0x800000
+#define FD_DBG_NOLRZ 0x1000000
 extern int fd_mesa_debug;
 extern bool fd_binning_enabled;