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spirv: Flip the tessellation winding order

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It's not SPIR-V that's backwards from GLSL, it's Vulkan that's backwards
from GL.  Let's make NIR consistent with the source language and do the
flipping inside the Vulkan driver instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand
2017-04-28 07:12:24 -07:00
parent 2891115671
commit fc91cbe20b
3 changed files with 15 additions and 8 deletions
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1
src/amd/vulkan/radv_pipeline.c
View File

@@ -262,6 +262,7 @@ radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
if (tcs_nir == NULL) if (tcs_nir == NULL)
return; return;
tes_nir->info.tess.ccw = !tes_nir->info.tess.ccw;
nir_lower_tes_patch_vertices(tes_nir, nir_lower_tes_patch_vertices(tes_nir,
tcs_nir->info.tess.tcs_vertices_out); tcs_nir->info.tess.tcs_vertices_out);

9
src/compiler/spirv/spirv_to_nir.c
View File

@@ -2951,17 +2951,12 @@ vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point,
case SpvExecutionModeVertexOrderCw: case SpvExecutionModeVertexOrderCw:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL || assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
b->shader->stage == MESA_SHADER_TESS_EVAL); b->shader->stage == MESA_SHADER_TESS_EVAL);
/* Vulkan's notion of CCW seems to match the hardware backends, b->shader->info.tess.ccw = false;
* but be the opposite of OpenGL. Currently NIR follows GL semantics,
* so we set it backwards here.
*/
b->shader->info.tess.ccw = true;
break; break;
case SpvExecutionModeVertexOrderCcw: case SpvExecutionModeVertexOrderCcw:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL || assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||
b->shader->stage == MESA_SHADER_TESS_EVAL); b->shader->stage == MESA_SHADER_TESS_EVAL);
/* Backwards; see above */ b->shader->info.tess.ccw = true;
b->shader->info.tess.ccw = false;
break; break;
case SpvExecutionModePointMode: case SpvExecutionModePointMode:
assert(b->shader->stage == MESA_SHADER_TESS_CTRL || assert(b->shader->stage == MESA_SHADER_TESS_CTRL ||

13
src/intel/vulkan/genX_pipeline.c
View File

@@ -1217,7 +1217,18 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) { anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
te.Partitioning = tes_prog_data->partitioning; te.Partitioning = tes_prog_data->partitioning;
te.OutputTopology = tes_prog_data->output_topology;
/* Vulkan has its winding order backwards from GL so TRI_CCW becomes
* TRI_CW and vice versa.
*/
if (tes_prog_data->output_topology == OUTPUT_TRI_CCW) {
te.OutputTopology = OUTPUT_TRI_CW;
} else if (tes_prog_data->output_topology == OUTPUT_TRI_CW) {
te.OutputTopology = OUTPUT_TRI_CCW;
} else {
te.OutputTopology = tes_prog_data->output_topology;
}
te.TEDomain = tes_prog_data->domain; te.TEDomain = tes_prog_data->domain;
te.TEEnable = true; te.TEEnable = true;
te.MaximumTessellationFactorOdd = 63.0; te.MaximumTessellationFactorOdd = 63.0;