From fc3fd7c69e80366b4510d9395decdfd83c63c99a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Sun, 4 Sep 2022 19:32:15 +0300 Subject: [PATCH] anv: dynamic color write mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This affects following packets: 3DSTATE_BLEND_STATE_POINTERS Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/vulkan/anv_pipeline.c | 8 -------- src/intel/vulkan/anv_private.h | 4 +--- src/intel/vulkan/gfx8_cmd_buffer.c | 11 ++++++----- 3 files changed, 7 insertions(+), 16 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e041a394510..b05ea876253 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -2302,14 +2302,6 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline, pipeline->patch_control_points = state->ts != NULL ? state->ts->patch_control_points : 0; - /* Store the color write masks, to be merged with color write enable if - * dynamic. - */ - if (state->cb != NULL) { - for (unsigned i = 0; i < state->cb->attachment_count; i++) - pipeline->color_comp_writes[i] = state->cb->attachments[i].write_mask; - } - return VK_SUCCESS; } diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 40fe759db9e..40e51a2dff9 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2954,8 +2954,6 @@ struct anv_graphics_pipeline { uint32_t patch_control_points; uint32_t rasterization_samples; - VkColorComponentFlags color_comp_writes[MAX_RTS]; - uint32_t view_mask; uint32_t instance_multiplier; @@ -3072,7 +3070,7 @@ anv_cmd_buffer_all_color_write_masked(const struct anv_cmd_buffer *cmd_buffer) /* Or all write masks are empty */ for (uint32_t i = 0; i < state->color_att_count; i++) { - if (state->pipeline->color_comp_writes[i] != 0) + if (dyn->cb.attachments[i].write_mask != 0) return false; } diff --git a/src/intel/vulkan/gfx8_cmd_buffer.c b/src/intel/vulkan/gfx8_cmd_buffer.c index 4f6a6cc1b5a..f64eefc0193 100644 --- a/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/src/intel/vulkan/gfx8_cmd_buffer.c @@ -532,7 +532,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) || BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) || BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) || - BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE)) { + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE) || + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) { const uint8_t color_writes = dyn->cb.color_write_enables; const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx; bool has_writeable_rt = @@ -572,16 +573,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) (color_writes & BITFIELD_BIT(i)) == 0; struct GENX(BLEND_STATE_ENTRY) entry = { .WriteDisableAlpha = write_disabled || - (pipeline->color_comp_writes[i] & + (dyn->cb.attachments[i].write_mask & VK_COLOR_COMPONENT_A_BIT) == 0, .WriteDisableRed = write_disabled || - (pipeline->color_comp_writes[i] & + (dyn->cb.attachments[i].write_mask & VK_COLOR_COMPONENT_R_BIT) == 0, .WriteDisableGreen = write_disabled || - (pipeline->color_comp_writes[i] & + (dyn->cb.attachments[i].write_mask & VK_COLOR_COMPONENT_G_BIT) == 0, .WriteDisableBlue = write_disabled || - (pipeline->color_comp_writes[i] & + (dyn->cb.attachments[i].write_mask & VK_COLOR_COMPONENT_B_BIT) == 0, .LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op], .LogicOpEnable = dyn->cb.logic_op_enable,