intel/blorp: Refactor the HiZ op interface

This commit does a few things:

 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix.
 2) Switch parameters to uint32_t to match the rest of blorp.
 3) Take a range of layers and loop internally.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

src/intel/blorp/blorp.c

@@ -286,8 +286,8 @@ blorp_ensure_sf_program(struct blorp_context *blorp,
 }
 
 void
-blorp_gen6_hiz_op(struct blorp_batch *batch,
-                  struct blorp_surf *surf, unsigned level, unsigned layer,
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
              enum blorp_hiz_op op)
 {
    struct blorp_params params;
@@ -295,15 +295,19 @@ blorp_gen6_hiz_op(struct blorp_batch *batch,
 
    params.hiz_op = op;
 
-   brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
-                               surf->surf->format, true);
+   for (uint32_t a = 0; a < num_layers; a++) {
+      const uint32_t layer = start_layer + a;
+
+      brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level,
+                                  layer, surf->surf->format, true);
 
       /* Align the rectangle primitive to 8x4 pixels.
        *
        * During fast depth clears, the emitted rectangle primitive  must be
        * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
-    * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
-    * PRM):
+       * 11.5.3.1 Depth Buffer Clear (and the matching section in the
+       * Sandybridge PRM):
+       *
        *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
        *     aligned to an 8x4 pixel block relative to the upper left corner
        *     of the depth buffer [...]
@@ -316,12 +320,12 @@ blorp_gen6_hiz_op(struct blorp_batch *batch,
        * hardware generations.
        *
        * However, for some miptree slices of a Z24 texture, emitting an 8x4
-    * aligned rectangle that covers the slice may clobber adjacent slices if
-    * we strictly adhered to the texture alignments specified in the PRM.  The
-    * Ivybridge PRM, Section "Alignment Unit Size", states that
-    * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
-    * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
-    * prevents the clobbering.
+       * aligned rectangle that covers the slice may clobber adjacent slices
+       * if we strictly adhered to the texture alignments specified in the
+       * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
+       * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
+       * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
+       * 8, which prevents the clobbering.
        */
       params.x1 = minify(params.depth.surf.logical_level0_px.width,
                          params.depth.view.base_level);
@@ -338,8 +342,10 @@ blorp_gen6_hiz_op(struct blorp_batch *batch,
 
       params.dst.surf.samples = params.depth.surf.samples;
       params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
-   params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
+      params.depth_format =
+         isl_format_get_depth_format(surf->surf->format, false);
       params.num_samples = params.depth.surf.samples;
 
       batch->blorp->exec(batch, &params);
    }
+}

src/intel/blorp/blorp.h

@@ -209,8 +209,8 @@ enum blorp_hiz_op {
 };
 
 void
-blorp_gen6_hiz_op(struct blorp_batch *batch,
-                  struct blorp_surf *surf, unsigned level, unsigned layer,
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+             uint32_t level, uint32_t start_layer, uint32_t num_layers,
              enum blorp_hiz_op op);
 
 #ifdef __cplusplus

src/intel/vulkan/anv_blorp.c

@@ -1723,6 +1723,6 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
 
    surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
 
-   blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
+   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
    blorp_batch_finish(&batch);
 }

src/mesa/drivers/dri/i965/brw_blorp.c

@@ -1074,8 +1074,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 
       struct blorp_batch batch;
       blorp_batch_init(&brw->blorp, &batch, brw, 0);
-      for (unsigned a = 0; a < num_layers; a++)
-         blorp_gen6_hiz_op(&batch, &surf, level, start_layer + a, op);
+      blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
       blorp_batch_finish(&batch);
    }