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amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji

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The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
This commit is contained in:
Nicolai Hähnle
2016-07-20 21:30:56 +02:00
committed by Marek Olšák
parent 145750efba
commit fbc9ba7559
8 changed files with 131 additions and 49 deletions
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12
src/amd/addrlib/core/addrlib1.cpp
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@@ -3228,13 +3228,14 @@ VOID Lib::PadDimensions(
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pPitchAlign, ///< [in,out] pitch align could be changed in HwlPadDimensions
UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
) const
{
UINT_32 pitchAlign = *pPitchAlign;
UINT_32 thickness = Thickness(tileMode);
ADDR_ASSERT(padDims <= 3);
@@ -3302,14 +3303,11 @@ VOID Lib::PadDimensions(
flags,
numSamples,
pTileInfo,
padDims,
mipLevel,
pPitch,
pitchAlign,
pHeight,
heightAlign,
pSlices,
sliceAlign);
pPitchAlign,
*pHeight,
heightAlign);
}

10
src/amd/addrlib/core/addrlib1.h
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@@ -71,6 +71,9 @@ struct TileModeFlags
UINT_32 isBankSwapped : 1;
};
static const UINT_32 Block64K = 0x10000;
static const UINT_32 PrtTileSize = Block64K;
/**
****************************************************************************************************
* @brief This class contains asic independent address lib functionalities
@@ -365,14 +368,13 @@ protected:
VOID PadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32* pPitchAlign, UINT_32 height, UINT_32 heightAlign) const
{
}

66
src/amd/addrlib/r800/ciaddrlib.cpp
View File

@@ -1939,6 +1939,41 @@ UINT_64 CiLib::HwlComputeMetadataNibbleAddress(
return metadataAddress;
}
/**
****************************************************************************************************
* CiLib::HwlComputeSurfaceAlignmentsMacroTiled
*
* @brief
* Hardware layer function to compute alignment request for macro tile mode
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 mipLevel, ///< [in] mip level
UINT_32 numSamples, ///< [in] number of samples
ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
UINT_32* pHeightAlign, ///< [out] height alignment in pixels
UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels
UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels
) const
{
if ((m_settings.isFiji == TRUE) &&
(flags.dccCompatible == TRUE) &&
(mipLevel == 0) &&
(tileMode == ADDR_TM_PRT_TILED_THIN1))
{
*pPitchAlign = PowTwoAlign(*pPitchAlign, 256);
}
}
/**
****************************************************************************************************
* CiLib::HwlPadDimensions
@@ -1956,22 +1991,19 @@ VOID CiLib::HwlPadDimensions(
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 numSamples, ///< [in] number of samples
ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32 padDims, ///< [in] Dimensions to pad valid value 1,2,3
UINT_32 mipLevel, ///< [in] MipLevel
ADDR_TILEINFO* pTileInfo, ///< [in] tile info
UINT_32 mipLevel, ///< [in] mip level
UINT_32* pPitch, ///< [in,out] pitch in pixels
UINT_32 pitchAlign, ///< [in] pitch alignment
UINT_32* pHeight, ///< [in,out] height in pixels
UINT_32 heightAlign, ///< [in] height alignment
UINT_32* pSlices, ///< [in,out] number of slices
UINT_32 sliceAlign ///< [in] number of slice alignment
UINT_32* pPitchAlign, ///< [in,out] pitch alignment
UINT_32 height, ///< [in] height in pixels
UINT_32 heightAlign ///< [in] height alignment
) const
{
if (m_settings.isVolcanicIslands &&
flags.dccCompatible &&
if ((m_settings.isVolcanicIslands == TRUE) &&
(flags.dccCompatible == TRUE) &&
(numSamples > 1) &&
(mipLevel == 0) &&
IsMacroTiled(tileMode))
(IsMacroTiled(tileMode) == TRUE))
{
UINT_32 tileSizePerSample = BITS_TO_BYTES(bpp * MicroTileWidth * MicroTileHeight);
UINT_32 samplesPerSplit = pTileInfo->tileSplitBytes / tileSizePerSample;
@@ -1979,7 +2011,7 @@ VOID CiLib::HwlPadDimensions(
if (samplesPerSplit < numSamples)
{
UINT_32 dccFastClearByteAlign = HwlGetPipes(pTileInfo) * m_pipeInterleaveBytes * 256;
UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * (*pHeight) * bpp * samplesPerSplit);
UINT_32 bytesPerSplit = BITS_TO_BYTES((*pPitch) * height * bpp * samplesPerSplit);
ADDR_ASSERT(IsPow2(dccFastClearByteAlign));
@@ -1988,15 +2020,14 @@ VOID CiLib::HwlPadDimensions(
UINT_32 dccFastClearPixelAlign = dccFastClearByteAlign /
BITS_TO_BYTES(bpp) /
samplesPerSplit;
UINT_32 macroTilePixelAlign = pitchAlign * heightAlign;
UINT_32 macroTilePixelAlign = (*pPitchAlign) * heightAlign;
if ((dccFastClearPixelAlign >= macroTilePixelAlign) &&
((dccFastClearPixelAlign % macroTilePixelAlign) == 0))
{
UINT_32 dccFastClearPitchAlignInMacroTile =
dccFastClearPixelAlign / macroTilePixelAlign;
UINT_32 heightInMacroTile = *pHeight / heightAlign;
UINT_32 dccFastClearPitchAlignInPixels;
UINT_32 heightInMacroTile = height / heightAlign;
while ((heightInMacroTile > 1) &&
((heightInMacroTile % 2) == 0) &&
@@ -2007,7 +2038,8 @@ VOID CiLib::HwlPadDimensions(
dccFastClearPitchAlignInMacroTile >>= 1;
}
dccFastClearPitchAlignInPixels = pitchAlign * dccFastClearPitchAlignInMacroTile;
UINT_32 dccFastClearPitchAlignInPixels =
(*pPitchAlign) * dccFastClearPitchAlignInMacroTile;
if (IsPow2(dccFastClearPitchAlignInPixels))
{
@@ -2019,6 +2051,8 @@ VOID CiLib::HwlPadDimensions(
*pPitch /= dccFastClearPitchAlignInPixels;
*pPitch *= dccFastClearPitchAlignInPixels;
}
*pPitchAlign = dccFastClearPitchAlignInPixels;
}
}
}

11
src/amd/addrlib/r800/ciaddrlib.h
View File

@@ -166,9 +166,14 @@ protected:
virtual VOID HwlPadDimensions(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 pitchAlign, UINT_32* pHeight, UINT_32 heightAlign,
UINT_32* pSlices, UINT_32 sliceAlign) const;
UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel,
UINT_32* pPitch, UINT_32 *PitchAlign, UINT_32 height, UINT_32 heightAlign) const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
private:
VOID ReadGbTileMode(

25
src/amd/addrlib/r800/egbaddrlib.cpp
View File

@@ -264,7 +264,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoLinear(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
&expPitch, pOut->pitchAlign,
&expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -378,7 +378,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
&expPitch, pOut->pitchAlign,
&expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -527,7 +527,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
&paddedPitch, pOut->pitchAlign,
&paddedPitch, &pOut->pitchAlign,
&paddedHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -932,22 +932,9 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
*pBaseAlign = pipes *
pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
if ((mipLevel == 0) && (flags.prt) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
{
static const UINT_32 PrtTileSize = 0x10000;
UINT_32 macroTileSize = macroTileWidth * macroTileHeight * numSamples * bpp / 8;
if (macroTileSize < PrtTileSize)
{
UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
*pPitchAlign *= numMacroTiles;
*pBaseAlign *= numMacroTiles;
}
}
HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples,
pTileInfo, pBaseAlign, pPitchAlign, pHeightAlign,
pMacroTileWidth, pMacroTileHeight);
}
return valid;

8
src/amd/addrlib/r800/egbaddrlib.h
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@@ -300,6 +300,14 @@ protected:
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const
{
}
private:
BOOL_32 ComputeSurfaceInfoLinear(

42
src/amd/addrlib/r800/siaddrlib.cpp
View File

@@ -3325,6 +3325,48 @@ ADDR_E_RETURNCODE SiLib::HwlGetMaxAlignments(
return ADDR_OK;
}
/**
****************************************************************************************************
* SiLib::HwlComputeSurfaceAlignmentsMacroTiled
*
* @brief
* Hardware layer function to compute alignment request for macro tile mode
*
* @return
* N/A
*
****************************************************************************************************
*/
VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 mipLevel, ///< [in] mip level
UINT_32 numSamples, ///< [in] number of samples
ADDR_TILEINFO* pTileInfo, ///< [in,out] bank structure.
UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
UINT_32* pHeightAlign, ///< [out] height alignment in pixels
UINT_32* pMacroTileWidth, ///< [out] macro tile width in pixels
UINT_32* pMacroTileHeight ///< [out] macro tile height in pixels
) const
{
if ((mipLevel == 0) && (flags.prt))
{
UINT_32 macroTileSize = (*pMacroTileWidth) * (*pMacroTileHeight) * numSamples * bpp / 8;
if (macroTileSize < PrtTileSize)
{
UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
*pPitchAlign *= numMacroTiles;
*pBaseAlign *= numMacroTiles;
}
}
}
/**
****************************************************************************************************
* SiLib::InitEquationTable

6
src/amd/addrlib/r800/siaddrlib.h
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@@ -241,6 +241,12 @@ protected:
virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const;
// Get equation table pointer and number of equations
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{