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nv50/ir: remove symbol table support for compute shaders

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The initial plan was to use this for OpenCL kernels, but back then the
plan was to convert from LLVM to TGSI. As it turns out, we didn't went
that way.

Right now for OpenCL we don't reqiure supporting multiple entry points
inside the same binary and if we want to support it later, we can add
this back.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4264>
This commit is contained in:
Karol Herbst
2019-07-04 18:36:27 +02:00
committed by Marge Bot
parent 83139aca59
commit fa8e628240
11 changed files with 5 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/nouveau/codegen/nv50_ir.h
View File

@@ -1323,8 +1323,6 @@ public:
const Target *getTarget() const { return target; }
private:
void emitSymbolTable(struct nv50_ir_prog_info *);
Type progType;
Target *target;

2
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
View File

@@ -100,8 +100,6 @@ struct nv50_ir_prog_info
const void *source;
void *relocData;
void *fixupData;
struct nv50_ir_prog_symbol *syms;
uint16_t numSyms;
} bin;
struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];

23
src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
View File

@@ -351,27 +351,6 @@ CodeEmitter::prepareEmission(BasicBlock *bb)
func->binSize += bb->binSize;
}
void
Program::emitSymbolTable(struct nv50_ir_prog_info *info)
{
unsigned int n = 0, nMax = allFuncs.getSize();
info->bin.syms =
(struct nv50_ir_prog_symbol *)MALLOC(nMax * sizeof(*info->bin.syms));
for (ArrayList::Iterator fi = allFuncs.iterator();
!fi.end();
fi.next(), ++n) {
Function *f = (Function *)fi.get();
assert(n < nMax);
info->bin.syms[n].label = f->getLabel();
info->bin.syms[n].offset = f->binPos;
}
info->bin.numSyms = n;
}
bool
Program::emitBinary(struct nv50_ir_prog_info *info)
{
@@ -411,8 +390,6 @@ Program::emitBinary(struct nv50_ir_prog_info *info)
info->bin.relocData = emit->getRelocInfo();
info->bin.fixupData = emit->getFixupInfo();
emitSymbolTable(info);
// the nvc0 driver will print the binary iself together with the header
if ((dbgFlags & NV50_IR_DEBUG_BASIC) && getTarget()->getChipset() < 0xc0)
emit->printBinary();

17
src/gallium/drivers/nouveau/nv50/nv50_compute.c
View File

@@ -225,21 +225,6 @@ nv50_compute_upload_input(struct nv50_context *nv50, const uint32_t *input)
}
}
static uint32_t
nv50_compute_find_symbol(struct nv50_context *nv50, uint32_t label)
{
struct nv50_program *prog = nv50->compprog;
const struct nv50_ir_prog_symbol *syms =
(const struct nv50_ir_prog_symbol *)prog->cp.syms;
unsigned i;
for (i = 0; i < prog->cp.num_syms; ++i) {
if (syms[i].label == label)
return prog->code_base + syms[i].offset;
}
return prog->code_base; /* no symbols or symbol not found */
}
void
nv50_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
{
@@ -258,7 +243,7 @@ nv50_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
nv50_compute_upload_input(nv50, info->input);
BEGIN_NV04(push, NV50_CP(CP_START_ID), 1);
PUSH_DATA (push, nv50_compute_find_symbol(nv50, info->pc));
PUSH_DATA (push, cp->code_base);
BEGIN_NV04(push, NV50_CP(SHARED_SIZE), 1);
PUSH_DATA (push, align(cp->cp.smem_size + cp->parm_size + 0x10, 0x40));

10
src/gallium/drivers/nouveau/nv50/nv50_program.c
View File

@@ -434,13 +434,6 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset,
prog->gp.vert_count = CLAMP(info->prop.gp.maxVertices, 1, 1024);
}
if (prog->type == PIPE_SHADER_COMPUTE) {
prog->cp.syms = info->bin.syms;
prog->cp.num_syms = info->bin.numSyms;
} else {
FREE(info->bin.syms);
}
if (prog->pipe.stream_output.num_outputs)
prog->so = nv50_program_create_strmout_state(info,
&prog->pipe.stream_output);
@@ -543,9 +536,6 @@ nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
FREE(p->interps);
FREE(p->so);
if (type == PIPE_SHADER_COMPUTE)
FREE(p->cp.syms);
memset(p, 0, sizeof(*p));
p->pipe = pipe;

2
src/gallium/drivers/nouveau/nv50/nv50_program.h
View File

@@ -104,8 +104,6 @@ struct nv50_program {
struct {
uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
uint32_t smem_size; /* shared memory (TGSI LOCAL resource) size */
void *syms;
unsigned num_syms;
} cp;
bool mul_zero_wins;

2
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
View File

@@ -437,7 +437,7 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
nvc0_compute_upload_input(nvc0, info);
BEGIN_NVC0(push, NVC0_CP(CP_START_ID), 1);
PUSH_DATA (push, nvc0_program_symbol_offset(cp, info->pc));
PUSH_DATA (push, cp->code_base);
BEGIN_NVC0(push, NVC0_CP(LOCAL_POS_ALLOC), 3);
PUSH_DATA (push, (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10));

2
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View File

@@ -326,8 +326,6 @@ bool nvc0_program_translate(struct nvc0_program *, uint16_t chipset,
bool nvc0_program_upload(struct nvc0_context *, struct nvc0_program *);
void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
void nvc0_program_library_upload(struct nvc0_context *);
uint32_t nvc0_program_symbol_offset(const struct nvc0_program *,
uint32_t label);
void nvc0_program_init_tcp_empty(struct nvc0_context *);
/* nvc0_shader_state.c */

21
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View File

@@ -638,8 +638,6 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
NOUVEAU_ERR("shader translation failed: %i\n", ret);
goto out;
}
if (prog->type != PIPE_SHADER_COMPUTE)
FREE(info->bin.syms);
prog->code = info->bin.code;
prog->code_size = info->bin.codeSize;
@@ -676,8 +674,6 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
ret = nvc0_fp_gen_header(prog, info);
break;
case PIPE_SHADER_COMPUTE:
prog->cp.syms = info->bin.syms;
prog->cp.num_syms = info->bin.numSyms;
break;
default:
ret = -1;
@@ -956,8 +952,6 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
FREE(prog->code); /* may be 0 for hardcoded shaders */
FREE(prog->relocs);
FREE(prog->fixups);
if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
FREE(prog->cp.syms);
if (prog->tfb) {
if (nvc0->state.tfb == prog->tfb)
nvc0->state.tfb = NULL;
@@ -970,21 +964,6 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
prog->type = type;
}
uint32_t
nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
{
const struct nv50_ir_prog_symbol *syms =
(const struct nv50_ir_prog_symbol *)prog->cp.syms;
unsigned base = 0;
unsigned i;
if (prog->type != PIPE_SHADER_COMPUTE)
base = GF100_SHADER_HEADER_SIZE;
for (i = 0; i < prog->cp.num_syms; ++i)
if (syms[i].label == label)
return prog->code_base + base + syms[i].offset;
return prog->code_base; /* no symbols or symbol not found */
}
void
nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
{

2
src/gallium/drivers/nouveau/nvc0/nvc0_program.h
View File

@@ -61,8 +61,6 @@ struct nvc0_program {
struct {
uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
uint32_t smem_size; /* shared memory (TGSI LOCAL resource) size */
void *syms;
unsigned num_syms;
} cp;
uint8_t num_barriers;

9
src/gallium/drivers/nouveau/nvc0/nve4_compute.c
View File

@@ -638,8 +638,7 @@ nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
NVA0C0_QMDV00_06_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);
NVA0C0_QMDV00_06_VAL_SET(qmd, SASS_VERSION, 0x30);
NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET,
nvc0_program_symbol_offset(cp, info->pc));
NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);
NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);
NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);
@@ -699,8 +698,7 @@ gp100_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
NVC0C0_QMDV02_01_DEF_SET(qmd, CWD_MEMBAR_TYPE, L1_SYSMEMBAR);
NVC0C0_QMDV02_01_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);
NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET,
nvc0_program_symbol_offset(cp, info->pc));
NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);
NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);
NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);
@@ -754,8 +752,7 @@ gv100_compute_setup_launch_desc(struct nvc0_context *nvc0, u32 *qmd,
{
struct nvc0_program *cp = nvc0->compprog;
struct nvc0_screen *screen = nvc0->screen;
uint64_t entry =
screen->text->offset + nvc0_program_symbol_offset(cp, info->pc);
uint64_t entry = screen->text->offset + cp->code_base;
NVC3C0_QMDV02_02_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
NVC3C0_QMDV02_02_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);