radv: Fix sampling from image layers of video decode target

Video decode target needs custom height alignment, but tex descriptor
still needs to be set to the original size the image was created with.
This makes the descriptor wrong for layer > 0, so we need to calculate
the layer offset and add it to bo address for this case.

Fixes: 5deb476095 ("radv: align video images internal width/height inside the driver.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3474978d52)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33113>

.pick_status.json

@@ -404,7 +404,7 @@
         "description": "radv: Fix sampling from image layers of video decode target",
         "nominated": true,
         "nomination_type": 2,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "5deb4760956f86369222cebef40a63a88ff9f5b8",
         "notes": null

src/amd/vulkan/radv_image.c

@@ -767,7 +767,7 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
                                 plane_height, image->vk.extent.depth, 0.0f, desc, NULL, NULL, NULL);
 
    radv_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, 0, 0, surface->blk_w, false, false, false,
-                                    false, desc, NULL);
+                                    false, desc, NULL, 0);
 
    ac_surface_compute_umd_metadata(&pdev->info, surface, image->vk.mip_levels, desc, &md->size_metadata, md->metadata,
                                    instance->debug_flags & RADV_DEBUG_EXTRA_MD);

src/amd/vulkan/radv_image_view.c

@@ -53,12 +53,12 @@ radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *
                                  const struct legacy_surf_level *base_level_info, unsigned plane_id,
                                  unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil,
                                  bool is_storage_image, bool disable_compression, bool enable_write_compression,
-                                 uint32_t *state, const struct ac_surf_nbc_view *nbc_view)
+                                 uint32_t *state, const struct ac_surf_nbc_view *nbc_view, uint64_t offset)
 {
    struct radv_image_plane *plane = &image->planes[plane_id];
    const uint32_t bind_idx = image->disjoint ? plane_id : 0;
    struct radv_image_binding *binding = &image->bindings[bind_idx];
-   uint64_t gpu_address = binding->bo ? radv_image_get_va(image, bind_idx) : 0;
+   uint64_t gpu_address = binding->bo ? radv_image_get_va(image, bind_idx) + offset : 0;
    const struct radv_physical_device *pdev = radv_device_physical(device);
 
    const struct ac_mutable_tex_state ac_state = {
@@ -371,6 +371,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
    union radv_descriptor *descriptor;
    uint32_t hw_level = iview->vk.base_mip_level;
    bool force_zero_base_mip = false;
+   uint64_t offset = 0;
 
    if (is_storage_image) {
       descriptor = &iview->storage_descriptor;
@@ -394,6 +395,13 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
 
          /* Clear the base array layer because addrlib adds it as part of the base addr offset. */
          first_layer = 0;
+      } else {
+         /* Video decode target uses custom height alignment. */
+         if (image->vk.usage & VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR) {
+            assert(image->planes[plane_id].surface.u.gfx9.swizzle_mode == 0);
+            offset += first_layer * image->planes[plane_id].surface.u.gfx9.surf_slice_size;
+            first_layer = 0;
+         }
       }
    } else {
       /* On GFX6-8, there are some cases where the view must use mip0 and minified image sizes:
@@ -421,6 +429,12 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
          extent.height = image->vk.extent.height;
          extent.depth = image->vk.extent.depth;
       }
+
+      /* Video decode target uses custom height alignment. */
+      if (image->vk.usage & VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR) {
+         offset += first_layer * image->planes[plane_id].surface.u.legacy.level[0].slice_size_dw * 4;
+         first_layer = 0;
+      }
    }
 
    radv_make_texture_descriptor(
@@ -447,7 +461,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
    radv_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id,
                                     force_zero_base_mip ? iview->vk.base_mip_level : 0, iview->vk.base_mip_level, blk_w,
                                     is_stencil, is_storage_image, disable_compression, enable_write_compression,
-                                    descriptor->plane_descriptors[descriptor_plane_id], &iview->nbc_view);
+                                    descriptor->plane_descriptors[descriptor_plane_id], &iview->nbc_view, offset);
 }
 
 /**

src/amd/vulkan/radv_image_view.h

@@ -66,7 +66,7 @@ void radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_im
                                       const struct legacy_surf_level *base_level_info, unsigned plane_id,
                                       unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil,
                                       bool is_storage_image, bool disable_compression, bool enable_write_compression,
-                                      uint32_t *state, const struct ac_surf_nbc_view *nbc_view);
+                                      uint32_t *state, const struct ac_surf_nbc_view *nbc_view, uint64_t offset);
 
 void radv_make_texture_descriptor(struct radv_device *device, struct radv_image *image, bool is_storage_image,
                                   VkImageViewType view_type, VkFormat vk_format, const VkComponentMapping *mapping,