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intel/dev: Add documentation about intel_device_info_pat_entry::mmap

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My initial understating was that L3_CACHE_POLICY would be the CPU
caching mode but that has nothing to do with CPU caching, it is the
GPU caching mode.

Due this miss understating we were using a not optimal PAT index that
will be fixed in the next patches, so to avoid such issues in future
adding comments to intel_device_info_pat_entry struct.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
This commit is contained in:
José Roberto de Souza
2024-06-27 13:17:24 -07:00
committed by Marge Bot
parent 4173e0f910
commit fa1129540a
1 changed files with 4 additions and 1 deletions
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5
src/intel/dev/intel_device_info.py
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@@ -156,7 +156,10 @@ Enum("intel_device_info_coherency_mode",
Struct("intel_device_info_pat_entry",
[Member("uint8_t", "index"),
Member("intel_device_info_mmap_mode", "mmap"),
Member("intel_device_info_mmap_mode", "mmap",
comment=dedent("""\
This tells KMD what caching mode the CPU mapping should use.
It has nothing to do with any PAT cache modes.""")),
Member("intel_device_info_coherency_mode", "coherency")])
Enum("intel_cmat_scope",