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i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

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v1: By Ben Widawsky <benjamin.widawsky@intel.com>
v2: v1 had an assert only for VS. Add the restriction for GS, HS and
    DS as well and make sure the allocated sizes are not multiple of 3.
v3: Move the entry_size checks in to compiler code (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Anuj Phogat
2016-01-05 08:41:39 -08:00
parent b76659997e
commit f9e31a26d4
5 changed files with 34 additions and 4 deletions
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11
src/intel/compiler/brw_vec4.cpp
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@@ -2839,10 +2839,17 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
const unsigned vue_entries =
MAX2(nr_attribute_slots, (unsigned)prog_data->base.vue_map.num_slots);
if (compiler->devinfo->gen == 6)
if (compiler->devinfo->gen == 6) {
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8);
else
} else {
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);
/* On Cannonlake software shall not program an allocation size that
* specifies a size that is a multiple of 3 64B (512-bit) cachelines.
*/
if (compiler->devinfo->gen == 10 &&
prog_data->base.urb_entry_size % 3 == 0)
prog_data->base.urb_entry_size++;
}
if (INTEL_DEBUG & DEBUG_VS) {
fprintf(stderr, "VS Output ");