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freedreno/a6xx: Add a few kernel regs/etc

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Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20925>
This commit is contained in:
Rob Clark
2023-01-18 13:53:45 -08:00
committed by Marge Bot
parent 4767ebeffc
commit f9bcf19e52
2 changed files with 25 additions and 3 deletions
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6
src/freedreno/.gitlab-ci/reference/crash.log
View File

@@ -20,10 +20,10 @@ bos:
size: 4096
registers:
00800005 RBBM_STATUS: { GPU_BUSY_IGN_AHB | CP_BUSY | CP_AHB_BUSY_CX_MASTER }
00000000 0x211: 00000000
00000000 0x212: 00000000
00000000 RBBM_STATUS1: 0
00000000 RBBM_STATUS2: 0
00000000 RBBM_STATUS3: { 0 }
8100430e 0x825: 8100430e
8100430e CP_STATUS_1: 0x8100430e
200a0000 VBIF_VERSION: 0x200a0000
00000000 VBIF_CLKON: { 0 }
00000000 0x3002: 00000000

22
src/freedreno/registers/adreno/a6xx.xml
View File

@@ -235,6 +235,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
<value value="0x70" name="A6XX_SP_LB_6_DATA"/>
<value value="0x71" name="A6XX_SP_LB_7_DATA"/>
<value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
</enum>
<enum name="a6xx_debugbus_id">
@@ -268,19 +271,32 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
<value value="0x22" name="A6XX_DBGBUS_RB_2"/>
<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
<value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
<value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
<value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
<value value="0x42" name="A6XX_DBGBUS_SP_2"/>
<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
<value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
<value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
<value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
<value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
<value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
<value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
<value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
<value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
</enum>
<enum name="a6xx_cp_perfcounter_select">
@@ -989,6 +1005,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x0821" name="CP_HW_FAULT"/>
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
<reg32 offset="0x0825" name="CP_STATUS_1"/>
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
<reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
@@ -1125,6 +1142,8 @@ to upconvert to 32b float internally?
<bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
<bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
</reg32>
<reg32 offset="0x0211" name="RBBM_STATUS1"/>
<reg32 offset="0x0212" name="RBBM_STATUS2"/>
<reg32 offset="0x0213" name="RBBM_STATUS3">
<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
</reg32>
@@ -1194,6 +1213,8 @@ to upconvert to 32b float internally?
<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
</reg32>
@@ -1377,6 +1398,7 @@ to upconvert to 32b float internally?
<bitfield high="7" low="0" name="PERFSEL"/>
</reg32>
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
<reg32 offset="0x3000" name="VBIF_VERSION"/>