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i965/gen6: Fix GPU hang when using stencil buffer without depth

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Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface.  From the Sandybridge
PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27
Tiled Surface:
   [DevGT+]: This field must be set to TRUE.

Fixes GPU hangs on the following Piglit tests:
   hiz-stencil-test-fbo-d0-s8
   hiz-stencil-read-fbo-d0-s8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Chad Versace
2011-11-23 10:06:46 -08:00
parent 8d15268a61
commit f99d5af03b
1 changed files with 5 additions and 0 deletions
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5
src/mesa/drivers/dri/i965/brw_misc_state.c
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@@ -278,6 +278,10 @@ static void emit_depthbuffer(struct brw_context *brw)
* *
* [DevGT]: This field must be set to the same value (enabled or * [DevGT]: This field must be set to the same value (enabled or
* disabled) as Hierarchical Depth Buffer Enable * disabled) as Hierarchical Depth Buffer Enable
*
* The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
* Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
* [DevGT+]: This field must be set to TRUE.
*/ */
struct intel_region *region = stencil_irb->mt->region; struct intel_region *region = stencil_irb->mt->region;
@@ -290,6 +294,7 @@ static void emit_depthbuffer(struct brw_context *brw)
(1 << 21) | /* separate stencil enable */ (1 << 21) | /* separate stencil enable */
(1 << 22) | /* hiz enable */ (1 << 22) | /* hiz enable */
(BRW_TILEWALK_YMAJOR << 26) | (BRW_TILEWALK_YMAJOR << 26) |
(1 << 27) | /* tiled surface */
(BRW_SURFACE_2D << 29)); (BRW_SURFACE_2D << 29));
OUT_BATCH(0); OUT_BATCH(0);
OUT_BATCH(((region->width - 1) << 6) | OUT_BATCH(((region->width - 1) << 6) |