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ac: add {tcs,tes}_patch_id to the abi

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Timothy Arceri
2017-12-06 13:30:33 +11:00
parent 15c6f3fdd5
commit f93740efc1
4 changed files with 16 additions and 19 deletions
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14
src/amd/common/ac_nir_to_llvm.c
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@@ -111,10 +111,8 @@ struct nir_to_llvm_context {
LLVMValueRef oc_lds; LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info; LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset; LLVMValueRef tess_factor_offset;
LLVMValueRef tcs_patch_id;
LLVMValueRef tcs_rel_ids; LLVMValueRef tcs_rel_ids;
LLVMValueRef tes_rel_patch_id; LLVMValueRef tes_rel_patch_id;
LLVMValueRef tes_patch_id;
LLVMValueRef tes_u; LLVMValueRef tes_u;
LLVMValueRef tes_v; LLVMValueRef tes_v;
@@ -684,7 +682,7 @@ declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u); add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v); add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id); add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_patch_id); add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
} }
static void static void
@@ -850,7 +848,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
&ctx->view_index); &ctx->view_index);
add_arg(&args, ARG_VGPR, ctx->ac.i32, add_arg(&args, ARG_VGPR, ctx->ac.i32,
&ctx->tcs_patch_id); &ctx->abi.tcs_patch_id);
add_arg(&args, ARG_VGPR, ctx->ac.i32, add_arg(&args, ARG_VGPR, ctx->ac.i32,
&ctx->tcs_rel_ids); &ctx->tcs_rel_ids);
@@ -878,7 +876,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
add_arg(&args, ARG_SGPR, ctx->ac.i32, add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tess_factor_offset); &ctx->tess_factor_offset);
add_arg(&args, ARG_VGPR, ctx->ac.i32, add_arg(&args, ARG_VGPR, ctx->ac.i32,
&ctx->tcs_patch_id); &ctx->abi.tcs_patch_id);
add_arg(&args, ARG_VGPR, ctx->ac.i32, add_arg(&args, ARG_VGPR, ctx->ac.i32,
&ctx->tcs_rel_ids); &ctx->tcs_rel_ids);
} }
@@ -4217,9 +4215,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
if (ctx->stage == MESA_SHADER_GEOMETRY) { if (ctx->stage == MESA_SHADER_GEOMETRY) {
result = ctx->abi->gs_prim_id; result = ctx->abi->gs_prim_id;
} else if (ctx->stage == MESA_SHADER_TESS_CTRL) { } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
result = ctx->nctx->tcs_patch_id; result = ctx->abi->tcs_patch_id;
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) { } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
result = ctx->nctx->tes_patch_id; result = ctx->abi->tes_patch_id;
} else } else
fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage); fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
break; break;
@@ -6542,7 +6540,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, ""); ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, ""); ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, ""); ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_rel_ids, ctx->rel_auto_id, "");
ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->tcs_patch_id, ctx->abi.vertex_id, ""); ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
} }
static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx) static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)

2
src/amd/common/ac_shader_abi.h
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@@ -42,6 +42,8 @@ struct ac_shader_abi {
LLVMValueRef draw_id; LLVMValueRef draw_id;
LLVMValueRef vertex_id; LLVMValueRef vertex_id;
LLVMValueRef instance_id; LLVMValueRef instance_id;
LLVMValueRef tcs_patch_id;
LLVMValueRef tes_patch_id;
LLVMValueRef gs_prim_id; LLVMValueRef gs_prim_id;
LLVMValueRef gs_invocation_id; LLVMValueRef gs_invocation_id;
LLVMValueRef frag_pos[4]; LLVMValueRef frag_pos[4];

17
src/gallium/drivers/radeonsi/si_shader.c
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@@ -763,11 +763,9 @@ static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
return LLVMGetParam(ctx->main_fn, return LLVMGetParam(ctx->main_fn,
ctx->param_vs_prim_id); ctx->param_vs_prim_id);
case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_CTRL:
return LLVMGetParam(ctx->main_fn, return ctx->abi.tcs_patch_id;
ctx->param_tcs_patch_id);
case PIPE_SHADER_TESS_EVAL: case PIPE_SHADER_TESS_EVAL:
return LLVMGetParam(ctx->main_fn, return ctx->abi.tes_patch_id;
ctx->param_tes_patch_id);
case PIPE_SHADER_GEOMETRY: case PIPE_SHADER_GEOMETRY:
return ctx->abi.gs_prim_id; return ctx->abi.gs_prim_id;
default: default:
@@ -3363,8 +3361,9 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES); 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR; unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
ret = si_insert_input_ret_float(ctx, ret, ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
ctx->param_tcs_patch_id, vgpr++); ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
vgpr++, "");
ret = si_insert_input_ret_float(ctx, ret, ret = si_insert_input_ret_float(ctx, ret,
ctx->param_tcs_rel_ids, vgpr++); ctx->param_tcs_rel_ids, vgpr++);
ctx->return_value = ret; ctx->return_value = ret;
@@ -4564,7 +4563,7 @@ static void declare_tes_input_vgprs(struct si_shader_context *ctx,
ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32); ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32); ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32); ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32); add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
} }
enum { enum {
@@ -4661,7 +4660,7 @@ static void create_function(struct si_shader_context *ctx)
ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32); ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
/* VGPRs */ /* VGPRs */
ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32); add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32); ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
/* param_tcs_offchip_offset and param_tcs_factor_offset are /* param_tcs_offchip_offset and param_tcs_factor_offset are
@@ -4700,7 +4699,7 @@ static void create_function(struct si_shader_context *ctx)
ctx->type == PIPE_SHADER_TESS_CTRL); ctx->type == PIPE_SHADER_TESS_CTRL);
/* VGPRs (first TCS, then VS) */ /* VGPRs (first TCS, then VS) */
ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32); add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32); ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
if (ctx->type == PIPE_SHADER_VERTEX) { if (ctx->type == PIPE_SHADER_VERTEX) {

2
src/gallium/drivers/radeonsi/si_shader_internal.h
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@@ -169,14 +169,12 @@ struct si_shader_context {
int param_tcs_factor_addr_base64k; int param_tcs_factor_addr_base64k;
int param_tcs_offchip_offset; int param_tcs_offchip_offset;
int param_tcs_factor_offset; int param_tcs_factor_offset;
int param_tcs_patch_id;
int param_tcs_rel_ids; int param_tcs_rel_ids;
/* API TES */ /* API TES */
int param_tes_u; int param_tes_u;
int param_tes_v; int param_tes_v;
int param_tes_rel_patch_id; int param_tes_rel_patch_id;
int param_tes_patch_id;
/* HW ES */ /* HW ES */
int param_es2gs_offset; int param_es2gs_offset;
/* API GS */ /* API GS */