softpipe: shortcircuit repeated lookups of the same tile
The sp_tile_cache is often called repeatedly to look up the same tile. Add a cache (to the cache) of the single tile most recently retreived and make a quick inline check to see if this matches the subsequent request. Add a tile_address bitfield struct to make this check easier.
This commit is contained in:
@@ -40,36 +40,6 @@
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#include "sp_texture.h"
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#include "sp_tile_cache.h"
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#define NUM_ENTRIES 50
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/** XXX move these */
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#define MAX_WIDTH 2048
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#define MAX_HEIGHT 2048
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struct softpipe_tile_cache
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{
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struct pipe_screen *screen;
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struct pipe_surface *surface; /**< the surface we're caching */
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struct pipe_transfer *transfer;
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void *transfer_map;
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struct pipe_texture *texture; /**< if caching a texture */
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unsigned timestamp;
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struct softpipe_cached_tile entries[NUM_ENTRIES];
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uint clear_flags[(MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32];
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float clear_color[4]; /**< for color bufs */
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uint clear_val; /**< for z+stencil, or packed color clear value */
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boolean depth_stencil; /**< Is the surface a depth/stencil format? */
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struct pipe_transfer *tex_trans;
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void *tex_trans_map;
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int tex_face, tex_level, tex_z;
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struct softpipe_cached_tile tile; /**< scratch tile for clears */
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};
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/**
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@@ -124,9 +94,9 @@ sp_create_tile_cache( struct pipe_screen *screen )
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if (tc) {
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tc->screen = screen;
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for (pos = 0; pos < NUM_ENTRIES; pos++) {
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tc->entries[pos].x =
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tc->entries[pos].y = -1;
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tc->entries[pos].addr.bits.invalid = 1;
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}
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tc->last_tile = &tc->entries[0]; /* any tile */
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}
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return tc;
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}
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@@ -244,7 +214,7 @@ sp_tile_cache_validate_texture(struct softpipe_tile_cache *tc)
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uint i;
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_debug_printf("INV %d %d\n", tc->timestamp, spt->timestamp);
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for (i = 0; i < NUM_ENTRIES; i++) {
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tc->entries[i].x = -3;
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tc->entries[i].addr.bits.invalid = 1;
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}
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tc->timestamp = spt->timestamp;
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@@ -281,7 +251,7 @@ sp_tile_cache_set_texture(struct softpipe_tile_cache *tc,
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/* mark as entries as invalid/empty */
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/* XXX we should try to avoid this when the teximage hasn't changed */
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for (i = 0; i < NUM_ENTRIES; i++) {
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tc->entries[i].x = -1;
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tc->entries[i].addr.bits.invalid = 1;
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}
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tc->tex_face = -1; /* any invalid value here */
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@@ -411,18 +381,22 @@ sp_flush_tile_cache(struct softpipe_tile_cache *tc)
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/* caching a drawing transfer */
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for (pos = 0; pos < NUM_ENTRIES; pos++) {
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struct softpipe_cached_tile *tile = tc->entries + pos;
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if (tile->x >= 0) {
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if (!tile->addr.bits.invalid) {
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if (tc->depth_stencil) {
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pipe_put_tile_raw(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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tile->data.depth32, 0/*STRIDE*/);
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}
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else {
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pipe_put_tile_rgba(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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(float *) tile->data.color);
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}
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tile->x = tile->y = -1; /* mark as empty */
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tile->addr.bits.invalid = 1; /* mark as empty */
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inuse++;
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}
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}
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@@ -434,7 +408,7 @@ sp_flush_tile_cache(struct softpipe_tile_cache *tc)
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else if (tc->texture) {
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/* caching a texture, mark all entries as empty */
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for (pos = 0; pos < NUM_ENTRIES; pos++) {
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tc->entries[pos].x = -1;
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tc->entries[pos].addr.bits.invalid = 1;
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}
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tc->tex_face = -1;
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}
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@@ -453,34 +427,34 @@ struct softpipe_cached_tile *
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sp_get_cached_tile(struct softpipe_tile_cache *tc, int x, int y)
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{
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struct pipe_transfer *pt = tc->transfer;
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/* tile pos in framebuffer: */
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const int tile_x = x & ~(TILE_SIZE - 1);
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const int tile_y = y & ~(TILE_SIZE - 1);
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union tile_address addr = tile_address( x, y, 0, 0, 0 );
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/* cache pos/entry: */
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const int pos = CACHE_POS(x, y);
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struct softpipe_cached_tile *tile = tc->entries + pos;
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if (tile_x != tile->x ||
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tile_y != tile->y) {
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if (addr.value != tile->addr.value) {
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if (tile->x >= 0) {
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if (tile->addr.bits.invalid == 0) {
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/* put dirty tile back in framebuffer */
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if (tc->depth_stencil) {
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pipe_put_tile_raw(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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tile->data.depth32, 0/*STRIDE*/);
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}
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else {
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pipe_put_tile_rgba(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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(float *) tile->data.color);
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}
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}
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tile->x = tile_x;
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tile->y = tile_y;
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tile->addr = addr;
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if (is_clear_flag_set(tc->clear_flags, x, y)) {
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/* don't get tile from framebuffer, just clear it */
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@@ -496,12 +470,16 @@ sp_get_cached_tile(struct softpipe_tile_cache *tc, int x, int y)
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/* get new tile data from transfer */
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if (tc->depth_stencil) {
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pipe_get_tile_raw(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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tile->data.depth32, 0/*STRIDE*/);
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}
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else {
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pipe_get_tile_rgba(pt,
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tile->x, tile->y, TILE_SIZE, TILE_SIZE,
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tile->addr.bits.x * TILE_SIZE,
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tile->addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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(float *) tile->data.color);
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}
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}
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@@ -519,36 +497,31 @@ sp_get_cached_tile(struct softpipe_tile_cache *tc, int x, int y)
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* XXX There's probably lots of ways in which we can improve this.
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*/
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static INLINE uint
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tex_cache_pos(int x, int y, int z, int face, int level)
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tex_cache_pos( union tile_address addr )
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{
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uint entry = x + y * 9 + z * 3 + face + level * 7;
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uint entry = (addr.bits.x +
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addr.bits.y * 9 +
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addr.bits.z * 3 +
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addr.bits.face +
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addr.bits.level * 7);
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return entry % NUM_ENTRIES;
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}
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/**
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* Similar to sp_get_cached_tile() but for textures.
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* Tiles are read-only and indexed with more params.
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*/
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const struct softpipe_cached_tile *
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sp_get_cached_tile_tex(struct softpipe_tile_cache *tc,
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int x, int y, int z,
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int face, int level)
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sp_find_cached_tile_tex(struct softpipe_tile_cache *tc,
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union tile_address addr )
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{
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struct pipe_screen *screen = tc->screen;
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/* tile pos in framebuffer: */
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const int tile_x = x & ~(TILE_SIZE - 1);
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const int tile_y = y & ~(TILE_SIZE - 1);
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/* cache pos/entry: */
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const uint pos = tex_cache_pos(x / TILE_SIZE, y / TILE_SIZE, z,
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face, level);
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struct softpipe_cached_tile *tile = tc->entries + pos;
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struct softpipe_cached_tile *tile;
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tile = tc->entries + tex_cache_pos( addr );
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if (tile_x != tile->x ||
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tile_y != tile->y ||
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z != tile->z ||
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face != tile->face ||
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level != tile->level) {
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if (addr.value != tile->addr.value) {
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/* cache miss. Most misses are because we've invaldiated the
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* texture cache previously -- most commonly on binding a new
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@@ -559,14 +532,14 @@ sp_get_cached_tile_tex(struct softpipe_tile_cache *tc,
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_debug_printf("miss at %u: x=%d y=%d z=%d face=%d level=%d\n"
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" tile %u: x=%d y=%d z=%d face=%d level=%d\n",
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pos, x/TILE_SIZE, y/TILE_SIZE, z, face, level,
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pos, tile->x, tile->y, tile->z, tile->face, tile->level);
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pos, tile->addr.bits.x, tile->addr.bits.y, tile->z, tile->face, tile->level);
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#endif
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/* check if we need to get a new transfer */
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if (!tc->tex_trans ||
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tc->tex_face != face ||
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tc->tex_level != level ||
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tc->tex_z != z) {
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tc->tex_face != addr.bits.face ||
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tc->tex_level != addr.bits.level ||
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tc->tex_z != addr.bits.z) {
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/* get new transfer (view into texture) */
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if (tc->tex_trans) {
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@@ -579,28 +552,32 @@ sp_get_cached_tile_tex(struct softpipe_tile_cache *tc,
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tc->tex_trans = NULL;
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}
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tc->tex_trans = screen->get_tex_transfer(screen, tc->texture, face, level, z,
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PIPE_TRANSFER_READ, 0, 0,
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tc->texture->width[level],
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tc->texture->height[level]);
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tc->tex_trans =
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screen->get_tex_transfer(screen, tc->texture,
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addr.bits.face,
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addr.bits.level,
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addr.bits.z,
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PIPE_TRANSFER_READ, 0, 0,
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tc->texture->width[addr.bits.level],
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tc->texture->height[addr.bits.level]);
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tc->tex_trans_map = screen->transfer_map(screen, tc->tex_trans);
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tc->tex_face = face;
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tc->tex_level = level;
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tc->tex_z = z;
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tc->tex_face = addr.bits.face;
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tc->tex_level = addr.bits.level;
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tc->tex_z = addr.bits.z;
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}
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/* get tile from the transfer (view into texture) */
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pipe_get_tile_rgba(tc->tex_trans,
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tile_x, tile_y, TILE_SIZE, TILE_SIZE,
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addr.bits.x * TILE_SIZE,
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addr.bits.y * TILE_SIZE,
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TILE_SIZE, TILE_SIZE,
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(float *) tile->data.color);
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tile->x = tile_x;
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tile->y = tile_y;
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tile->z = z;
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tile->face = face;
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tile->level = level;
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tile->addr = addr;
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}
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tc->last_tile = tile;
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return tile;
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}
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@@ -633,6 +610,6 @@ sp_tile_cache_clear(struct softpipe_tile_cache *tc, const float *rgba,
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for (pos = 0; pos < NUM_ENTRIES; pos++) {
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struct softpipe_cached_tile *tile = tc->entries + pos;
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tile->x = tile->y = -1;
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tile->addr.bits.invalid = 1;
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}
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}
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