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replace _mesa_logbase2 with util_logbase2

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
This commit is contained in:
Dylan Baker
2019-12-06 09:20:09 -08:00
parent e190e8cef2
commit f8e4542bad
11 changed files with 18 additions and 38 deletions
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4
src/intel/compiler/brw_eu_emit.c
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@@ -593,7 +593,7 @@ gen7_set_dp_scratch_message(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(devinfo->gen >= 8 && num_regs == 8));
const unsigned block_size = (devinfo->gen >= 8 ? _mesa_logbase2(num_regs) :
const unsigned block_size = (devinfo->gen >= 8 ? util_logbase2(num_regs) :
num_regs - 1);
brw_set_desc(p, inst, brw_message_desc(
@@ -3421,7 +3421,7 @@ brw_broadcast(struct brw_codegen *p,
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);
brw_SHL(p, addr, vec1(idx),
brw_imm_ud(_mesa_logbase2(type_sz(src.type)) +
brw_imm_ud(util_logbase2(type_sz(src.type)) +
src.hstride - 1));
/* We can only address up to limit bytes using the indirect

2
src/intel/compiler/brw_fs.cpp
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@@ -6297,7 +6297,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
/* Only power-of-two execution sizes are representable in the instruction
* control fields.
*/
return 1 << _mesa_logbase2(max_width);
return 1 << util_logbase2(max_width);
}
/**

2
src/intel/compiler/brw_fs_generator.cpp
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@@ -587,7 +587,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);
brw_SHL(p, addr, group_idx,
brw_imm_uw(_mesa_logbase2(type_sz(src.type)) +
brw_imm_uw(util_logbase2(type_sz(src.type)) +
src.hstride - 1));
/* Add on the register start offset */

4
src/intel/compiler/brw_fs_reg_allocate.cpp
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@@ -86,7 +86,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
{
const struct gen_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
const int index = _mesa_logbase2(dispatch_width / 8);
const int index = util_logbase2(dispatch_width / 8);
if (dispatch_width > 8 && devinfo->gen >= 7) {
/* For IVB+, we don't need the PLN hacks or the even-reg alignment in
@@ -423,7 +423,7 @@ public:
* for reg_width == 2.
*/
int reg_width = fs->dispatch_width / 8;
rsi = _mesa_logbase2(reg_width);
rsi = util_logbase2(reg_width);
payload_node_count = ALIGN(fs->first_non_payload_grf, reg_width);
/* Get payload IP information */

4
src/intel/compiler/brw_ir_fs.h
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@@ -298,8 +298,8 @@ subscript(fs_reg reg, brw_reg_type type, unsigned i)
/* The stride is encoded inconsistently for fixed GRF and ARF registers
* as the log2 of the actual vertical and horizontal strides.
*/
const int delta = _mesa_logbase2(type_sz(reg.type)) -
_mesa_logbase2(type_sz(type));
const int delta = util_logbase2(type_sz(reg.type)) -
util_logbase2(type_sz(type));
reg.hstride += (reg.hstride ? delta : 0);
reg.vstride += (reg.vstride ? delta : 0);