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freedreno/regs: add bit to control continuous clock with 7nm PHYs

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7nm PHYs need another special bit set in DSI_LANE_CTRL to enable
continuous DSI clock. Document this bit.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11219>
This commit is contained in:
Dmitry Baryshkov
2021-06-07 16:14:39 +03:00
committed by Marge Bot
parent fd9310f885
commit f800b9182b
1 changed files with 1 additions and 0 deletions
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src/freedreno/registers/dsi/dsi.xml
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@@ -271,6 +271,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
</reg32>
<reg32 offset="0x000a8" name="LANE_CTRL">
<bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
<bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
</reg32>
<reg32 offset="0x000ac" name="LANE_SWAP_CTRL">