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freedreno: deduplicate a3xx+ disasm

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Merge the extra tracking that is useful for generating stats from asm
(as opposed to ir), and for guestimating things like inputs and outputs
(mostly useful for r/e) into ir3's version and drop cffdec's version.

There is a small change in disasm output for the decode tools, in that
it no longer prints the used consts, but rather just the max accessed
const.  This is the more useful piece of information, and avoids making
the shared regmask type big enough to deal with the const reg file.
Additional error checking for invalid regids causes crashdec to bail
out sooner when decoding memory that *might* hold valid instructions.
Also, crashdec no longer prints stats, because stats aren't very useful
when trying to decode random instruction memory (which might or might
not be valid instructions).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>
This commit is contained in:
Rob Clark
2020-07-25 10:28:42 -07:00
committed by Marge Bot
parent 6b379a4cb4
commit f7bd3456d7
24 changed files with 424 additions and 4012 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1055
src/freedreno/.gitlab-ci/reference/crash.log
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File diff suppressed because it is too large Load Diff

36
src/freedreno/.gitlab-ci/reference/fd-clouds.log
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@@ -640,8 +640,8 @@ t4 write SP_VS_OBJ_START_LO (a81c)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -662,8 +662,8 @@ t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -1110,8 +1110,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -1955,8 +1955,8 @@ t4 write SP_VS_OBJ_START_LO (a81c)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -1977,8 +1977,8 @@ t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -3498,8 +3498,8 @@ t4 write SP_FS_OBJ_START_LO (a983)
- used (merged): 0-147 (cnt=148, max=147)
- input (half): (cnt=0, max=0)
- input (full): 19-20 (cnt=2, max=20)
- const (half): (cnt=0, max=0)
- const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113)
- max const: 113
- output (half): (cnt=0, max=0) (estimated)
- output (full): 4-7 (cnt=4, max=7) (estimated)
- shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full
@@ -4921,8 +4921,8 @@ t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
- used (merged): 0-147 (cnt=148, max=147)
- input (half): (cnt=0, max=0)
- input (full): 19-20 (cnt=2, max=20)
- const (half): (cnt=0, max=0)
- const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113)
- max const: 113
- output (half): (cnt=0, max=0) (estimated)
- output (full): 4-7 (cnt=4, max=7) (estimated)
- shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full
@@ -5335,8 +5335,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -6773,8 +6773,8 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- used (merged): 0-147 (cnt=148, max=147)
- input (half): (cnt=0, max=0)
- input (full): 19-20 (cnt=2, max=20)
- const (half): (cnt=0, max=0)
- const (full): 0-1 3-5 8-9 32-113 (cnt=89, max=113)
- max const: 113
- output (half): (cnt=0, max=0) (estimated)
- output (full): 4-7 (cnt=4, max=7) (estimated)
- shaderdb: 2414 instructions, 1355 nops, 1059 non-nops, (1406 instlen), 0 half, 19 full

134
src/freedreno/.gitlab-ci/reference/glxgears-a420.log
View File

@@ -427,11 +427,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): (cnt=0, max=0)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -453,11 +452,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 (cnt=4, max=3)
- used (merged): 0-7 (cnt=8, max=7)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): 0-3 (cnt=4, max=3)
- max const: 3
- output (half): (cnt=0, max=0) (estimated)
- output (full): 0-3 (cnt=4, max=3) (estimated)
- shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full
@@ -1041,11 +1039,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-13 (cnt=14, max=13)
- used (merged): 0-27 (cnt=28, max=27)
- input (half): (cnt=0, max=0)
- input (full): 2-5 (cnt=4, max=5)
- const (half): (cnt=0, max=0)
- const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 6-13 (cnt=8, max=13) (estimated)
- shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
@@ -1082,14 +1079,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109ce878: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -1673,11 +1669,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -1713,14 +1708,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109cf040: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -2106,11 +2100,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -2145,11 +2138,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0 2-5 (cnt=5, max=5)
- used (merged): 0-1 4-11 (cnt=10, max=11)
- input (half): (cnt=0, max=0)
- input (full): 0 (cnt=1, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 2-5 (cnt=4, max=5) (estimated)
- shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
@@ -2500,11 +2492,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-13 (cnt=14, max=13)
- used (merged): 0-27 (cnt=28, max=27)
- input (half): (cnt=0, max=0)
- input (full): 2-5 (cnt=4, max=5)
- const (half): (cnt=0, max=0)
- const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 6-13 (cnt=8, max=13) (estimated)
- shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
@@ -2541,14 +2532,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109cfb78: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -3055,11 +3045,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -3095,14 +3084,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109d02c0: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -3488,11 +3476,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -3527,11 +3514,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0 2-5 (cnt=5, max=5)
- used (merged): 0-1 4-11 (cnt=10, max=11)
- input (half): (cnt=0, max=0)
- input (full): 0 (cnt=1, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 2-5 (cnt=4, max=5) (estimated)
- shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
@@ -3882,11 +3868,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-13 (cnt=14, max=13)
- used (merged): 0-27 (cnt=28, max=27)
- input (half): (cnt=0, max=0)
- input (full): 2-5 (cnt=4, max=5)
- const (half): (cnt=0, max=0)
- const (full): 0-18 20-26 32-34 36-38 40-42 52 (cnt=36, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 6-13 (cnt=8, max=13) (estimated)
- shaderdb: 74 instructions, 38 nops, 36 non-nops, (61 instlen), 0 half, 4 full
@@ -3923,14 +3908,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109d0df8: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -4437,11 +4421,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -4477,14 +4460,13 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
:0:0010:0010[00000000x_00000000x] nop
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 252 (cnt=5, max=3)
- used (merged): 0-7 504-505 (cnt=10, max=7)
- used (full): 0-3 (cnt=4, max=3)
- input (half): (cnt=0, max=0)
- input (full): 0-3 (cnt=4, max=3)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 252 (cnt=1, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 11 instructions, 5 nops, 6 non-nops, (11 instlen), 0 half, 1 full
- shaderdb: 1 (ss), 0 (sy)
109d1540: 0000: c0213000 00700000 00000000 00000000 00000000 01c00000 c7c60000 01c00002
@@ -4870,11 +4852,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (131 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-8 10-17 (cnt=17, max=17)
- used (merged): 0-17 20-35 (cnt=34, max=35)
- input (half): (cnt=0, max=0)
- input (full): 2-8 (cnt=7, max=8)
- const (half): (cnt=0, max=0)
- const (full): 0-22 28-30 32-34 36-38 52 (cnt=33, max=52)
- max const: 52
- output (half): (cnt=0, max=0) (estimated)
- output (full): 10-17 (cnt=8, max=17) (estimated)
- shaderdb: 67 instructions, 31 nops, 36 non-nops, (56 instlen), 0 half, 5 full
@@ -4909,11 +4890,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0 2-5 (cnt=5, max=5)
- used (merged): 0-1 4-11 (cnt=10, max=11)
- input (half): (cnt=0, max=0)
- input (full): 0 (cnt=1, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): 2-5 (cnt=4, max=5) (estimated)
- shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 0 half, 2 full
@@ -5214,11 +5194,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): (cnt=0, max=0)
- used (merged): (cnt=0, max=0)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): (cnt=0, max=0)
- max const: 0
- output (half): (cnt=0, max=0) (estimated)
- output (full): (cnt=0, max=0) (estimated)
- shaderdb: 5 instructions, 4 nops, 1 non-nops, (5 instlen), 0 half, 0 full
@@ -5240,11 +5219,10 @@ t3 opcode: CP_LOAD_STATE4 (30) (35 dwords)
Register Stats:
- used (half): (cnt=0, max=0)
- used (full): 0-3 (cnt=4, max=3)
- used (merged): 0-7 (cnt=8, max=7)
- input (half): (cnt=0, max=0)
- input (full): (cnt=0, max=0)
- const (half): (cnt=0, max=0)
- const (full): 0-3 (cnt=4, max=3)
- max const: 3
- output (half): (cnt=0, max=0) (estimated)
- output (full): 0-3 (cnt=4, max=3) (estimated)
- shaderdb: 9 instructions, 8 nops, 1 non-nops, (9 instlen), 0 half, 1 full

9
src/freedreno/decode/disasm.h → src/freedreno/common/disasm.h
View File

@@ -24,6 +24,8 @@
#ifndef DISASM_H_
#define DISASM_H_
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include "compiler/shader_enums.h"
@@ -32,7 +34,8 @@
enum debug_t {
PRINT_RAW = 0x1, /* dump raw hexdump */
PRINT_VERBOSE = 0x2,
EXPAND_REPEAT = 0x4,
PRINT_STATS = 0x4,
EXPAND_REPEAT = 0x8,
};
struct shader_stats {
@@ -47,6 +50,8 @@ int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage typ
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
unsigned gpu_id, struct shader_stats *stats);
void disasm_set_debug(enum debug_t debug);
void disasm_a2xx_set_debug(enum debug_t debug);
void disasm_a3xx_set_debug(enum debug_t debug);
#endif /* DISASM_H_ */

1
src/freedreno/common/meson.build
View File

@@ -21,6 +21,7 @@
libfreedreno_common = static_library(
'freedreno_common',
[
'disasm.h',
'freedreno_uuid.c',
'freedreno_uuid.h',
'freedreno_guardband.h',

6
src/freedreno/decode/cffdump.c
View File

@@ -139,6 +139,7 @@ static const struct option opts[] = {
int main(int argc, char **argv)
{
enum debug_t debug = PRINT_RAW | PRINT_STATS;
int ret = -1;
int start = 0, end = 0x7ffffff, draw = -1;
int c;
@@ -153,7 +154,7 @@ int main(int argc, char **argv)
/* option that set a flag, nothing to do */
break;
case 'v':
disasm_set_debug(PRINT_RAW | EXPAND_REPEAT | PRINT_VERBOSE);
debug |= (PRINT_RAW | EXPAND_REPEAT | PRINT_VERBOSE);
break;
case 's':
options.summary = true;
@@ -192,6 +193,9 @@ int main(int argc, char **argv)
}
}
disasm_a2xx_set_debug(debug);
disasm_a3xx_set_debug(debug);
if (interactive) {
pager_open();
}

6
src/freedreno/decode/crashdec.c
View File

@@ -55,7 +55,7 @@
#include "pager.h"
#include "rnnutil.h"
#include "util.h"
#include "instr-a3xx.h"
#include "ir3/instr-a3xx.h"
static FILE *in;
@@ -223,7 +223,7 @@ void
ir3_assert_handler(const char *expr, const char *file, int line,
const char *func)
{
printf("%s:%u: %s: Assertion `%s' failed.\n", file, line, func, expr);
printf("\n%s:%u: %s: Assertion `%s' failed.\n", file, line, func, expr);
if (jmp_env_valid)
longjmp(jmp_env, 1);
abort();
@@ -1103,6 +1103,8 @@ main(int argc, char **argv)
}
}
disasm_a3xx_set_debug(PRINT_RAW);
if (interactive) {
pager_open();
}

4
src/freedreno/decode/disasm-a2xx.c
View File

@@ -49,7 +49,7 @@ static const char *levels[] = {
"x",
};
enum debug_t debug;
static enum debug_t debug;
static struct rnn *rnn;
@@ -618,7 +618,7 @@ int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage typ
return 0;
}
void disasm_set_debug(enum debug_t d)
void disasm_a2xx_set_debug(enum debug_t d)
{
debug = d;
}

1641
src/freedreno/decode/disasm-a3xx.c
View File

File diff suppressed because it is too large Load Diff

1115
src/freedreno/decode/instr-a3xx.h
View File

File diff suppressed because it is too large Load Diff

15
src/freedreno/decode/meson.build
View File

@@ -37,10 +37,7 @@ libfreedreno_cffdec = static_library(
'cffdec.c',
'cffdec.h',
'disasm-a2xx.c',
'disasm-a3xx.c',
'disasm.h',
'instr-a2xx.h',
'instr-a3xx.h',
'pager.c',
'pager.h',
'rnnutil.c',
@@ -48,6 +45,7 @@ libfreedreno_cffdec = static_library(
'util.h',
],
include_directories: [
inc_freedreno,
inc_freedreno_rnn,
inc_include,
inc_src,
@@ -55,7 +53,10 @@ libfreedreno_cffdec = static_library(
c_args : [ no_override_init_args ],
gnu_symbol_visibility: 'hidden',
dependencies: [],
link_with: libfreedreno_rnn,
link_with: [
libfreedreno_rnn,
libfreedreno_ir3, # for disasm_a3xx
],
build_by_default: false,
)
@@ -85,6 +86,7 @@ if dep_lua.found() and dep_libarchive.found()
'script.h'
],
include_directories: [
inc_freedreno,
inc_freedreno_rnn,
inc_include,
inc_src,
@@ -107,6 +109,7 @@ crashdec = executable(
'crashdec',
'crashdec.c',
include_directories: [
inc_freedreno,
inc_freedreno_rnn,
inc_include,
inc_src,
@@ -125,6 +128,7 @@ if dep_libarchive.found()
'pgmdump',
'pgmdump.c',
include_directories: [
inc_freedreno,
inc_include,
inc_src,
],
@@ -133,6 +137,7 @@ if dep_libarchive.found()
link_with: [
libfreedreno_cffdec,
libfreedreno_io,
libfreedreno_ir3, # for disasm_a3xx
],
build_by_default: with_tools.contains('freedreno'),
install: false,
@@ -141,6 +146,7 @@ if dep_libarchive.found()
'pgmdump2',
'pgmdump2.c',
include_directories: [
inc_freedreno,
inc_include,
inc_src,
],
@@ -149,6 +155,7 @@ if dep_libarchive.found()
link_with: [
libfreedreno_cffdec,
libfreedreno_io,
libfreedreno_ir3, # for disasm_a3xx
],
build_by_default: with_tools.contains('freedreno'),
install: false,

5
src/freedreno/decode/pgmdump.c
View File

@@ -891,7 +891,7 @@ static void dump_program(struct state *state)
int main(int argc, char **argv)
{
enum rd_sect_type type = RD_NONE;
enum debug_t debug = 0;
enum debug_t debug = PRINT_RAW | PRINT_STATS;
void *buf = NULL;
int sz;
struct io *io;
@@ -945,7 +945,8 @@ int main(int argc, char **argv)
return -1;
}
disasm_set_debug(debug);
disasm_a2xx_set_debug(debug);
disasm_a3xx_set_debug(debug);
infile = argv[1];

4
src/freedreno/decode/pgmdump2.c
View File

@@ -440,7 +440,7 @@ static void dump_program(struct state *state)
int main(int argc, char **argv)
{
enum rd_sect_type type = RD_NONE;
enum debug_t debug = 0;
enum debug_t debug = PRINT_RAW | PRINT_STATS;
void *buf = NULL;
int sz;
struct io *io;
@@ -494,7 +494,7 @@ int main(int argc, char **argv)
return -1;
}
disasm_set_debug(debug);
disasm_a3xx_set_debug(debug);
infile = argv[1];

266
src/freedreno/ir3/disasm-a3xx.c
View File

@@ -30,14 +30,9 @@
#include <util/u_debug.h>
#include "disasm.h"
#include "instr-a3xx.h"
/* bitmask of debug flags */
enum debug_t {
PRINT_RAW = 0x1, /* dump raw hexdump */
PRINT_VERBOSE = 0x2,
EXPAND_REPEAT = 0x4,
};
#include "regmask.h"
static enum debug_t debug;
@@ -80,12 +75,28 @@ struct disasm_ctx {
int level;
unsigned gpu_id;
struct shader_stats *stats;
/* we have to process the dst register after src to avoid tripping up
* the read-before-write detection
*/
unsigned last_dst;
bool last_dst_full;
bool last_dst_valid;
/* current instruction repeat flag: */
unsigned repeat;
/* current instruction repeat indx/offset (for --expand): */
unsigned repeatidx;
unsigned instructions;
/* tracking for register usage */
struct {
regmask_t used;
regmask_t used_merged;
regmask_t rbw; /* read before write */
regmask_t war; /* write after read */
unsigned max_const;
} regs;
};
static const char *float_imms[] = {
@@ -157,6 +168,24 @@ static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
}
}
static void regmask_set(regmask_t *regmask, unsigned num, bool full)
{
ir3_assert(num < MAX_REG);
__regmask_set(regmask, !full, num);
}
static void regmask_clear(regmask_t *regmask, unsigned num, bool full)
{
ir3_assert(num < MAX_REG);
__regmask_clear(regmask, !full, num);
}
static unsigned regmask_get(regmask_t *regmask, unsigned num, bool full)
{
ir3_assert(num < MAX_REG);
return __regmask_get(regmask, !full, num);
}
static unsigned regidx(reg_t reg)
{
return (4 * reg.num) + reg.comp;
@@ -170,8 +199,127 @@ static reg_t idxreg(unsigned idx)
};
}
static void print_sequence(struct disasm_ctx *ctx, int first, int last)
{
if (first != MAX_REG) {
if (first == last) {
fprintf(ctx->out, " %d", first);
} else {
fprintf(ctx->out, " %d-%d", first, last);
}
}
}
static int print_regs(struct disasm_ctx *ctx, regmask_t *regmask, bool full)
{
int num, max = 0, cnt = 0;
int first, last;
first = last = MAX_REG;
for (num = 0; num < MAX_REG; num++) {
if (regmask_get(regmask, num, full)) {
if (num != (last + 1)) {
print_sequence(ctx, first, last);
first = num;
}
last = num;
if (num < (48*4))
max = num;
cnt++;
}
}
print_sequence(ctx, first, last);
fprintf(ctx->out, " (cnt=%d, max=%d)", cnt, max);
return max;
}
static void print_reg_stats(struct disasm_ctx *ctx)
{
int fullreg, halfreg;
fprintf(ctx->out, "%sRegister Stats:\n", levels[ctx->level]);
fprintf(ctx->out, "%s- used (half):", levels[ctx->level]);
halfreg = print_regs(ctx, &ctx->regs.used, false);
fprintf(ctx->out, "\n");
fprintf(ctx->out, "%s- used (full):", levels[ctx->level]);
fullreg = print_regs(ctx, &ctx->regs.used, true);
fprintf(ctx->out, "\n");
if (ctx->gpu_id >= 600) {
fprintf(ctx->out, "%s- used (merged):", levels[ctx->level]);
print_regs(ctx, &ctx->regs.used_merged, false);
fprintf(ctx->out, "\n");
}
fprintf(ctx->out, "%s- input (half):", levels[ctx->level]);
print_regs(ctx, &ctx->regs.rbw, false);
fprintf(ctx->out, "\n");
fprintf(ctx->out, "%s- input (full):", levels[ctx->level]);
print_regs(ctx, &ctx->regs.rbw, true);
fprintf(ctx->out, "\n");
fprintf(ctx->out, "%s- max const: %u\n", levels[ctx->level], ctx->regs.max_const);
fprintf(ctx->out, "\n");
fprintf(ctx->out, "%s- output (half):", levels[ctx->level]);
print_regs(ctx, &ctx->regs.war, false);
fprintf(ctx->out, " (estimated)\n");
fprintf(ctx->out, "%s- output (full):", levels[ctx->level]);
print_regs(ctx, &ctx->regs.war, true);
fprintf(ctx->out, " (estimated)\n");
/* convert to vec4, which is the granularity that registers are
* assigned to shader:
*/
fullreg = (fullreg + 3) / 4;
halfreg = (halfreg + 3) / 4;
// Note this count of instructions includes rptN, which matches
// up to how mesa prints this:
fprintf(ctx->out, "%s- shaderdb: %d instructions, %d nops, %d non-nops, "
"(%d instlen), %d half, %d full\n",
levels[ctx->level], ctx->stats->instructions, ctx->stats->nops,
ctx->stats->instructions - ctx->stats->nops, ctx->stats->instlen,
halfreg, fullreg);
fprintf(ctx->out, "%s- shaderdb: %d (ss), %d (sy)\n", levels[ctx->level],
ctx->stats->ss, ctx->stats->sy);
}
static void process_reg_dst(struct disasm_ctx *ctx)
{
if (!ctx->last_dst_valid)
return;
/* ignore dummy writes (ie. r63.x): */
if (!VALIDREG(ctx->last_dst))
return;
for (unsigned i = 0; i <= ctx->repeat; i++) {
unsigned dst = ctx->last_dst + i;
regmask_set(&ctx->regs.war, dst, ctx->last_dst_full);
regmask_set(&ctx->regs.used, dst, ctx->last_dst_full);
if (ctx->gpu_id >= 600) {
if (ctx->last_dst_full) {
regmask_set(&ctx->regs.used_merged, (dst*2)+0, false);
regmask_set(&ctx->regs.used_merged, (dst*2)+1, false);
} else {
regmask_set(&ctx->regs.used_merged, dst, false);
}
}
}
ctx->last_dst_valid = false;
}
static void print_reg_dst(struct disasm_ctx *ctx, reg_t reg, bool full, bool addr_rel)
{
/* presumably the special registers a0.c and p0.c don't count.. */
if (!(addr_rel || (reg.num == REG_A0) || (reg.num == REG_P0))) {
ctx->last_dst = regidx(reg);
ctx->last_dst_full = full;
ctx->last_dst_valid = true;
}
reg = idxreg(regidx(reg) + ctx->repeatidx);
print_reg(ctx, reg, full, false, false, false, false, false, false, addr_rel);
}
@@ -196,6 +344,45 @@ static void print_src(struct disasm_ctx *ctx, struct reginfo *info)
{
reg_t reg = info->reg;
/* presumably the special registers a0.c and p0.c don't count.. */
if (!(info->addr_rel || info->c || info->im ||
(reg.num == REG_A0) || (reg.num == REG_P0))) {
int i, num = regidx(reg);
for (i = 0; i <= ctx->repeat; i++) {
unsigned src = num + i;
if (!regmask_get(&ctx->regs.used, src, info->full))
regmask_set(&ctx->regs.rbw, src, info->full);
regmask_clear(&ctx->regs.war, src, info->full);
regmask_set(&ctx->regs.used, src, info->full);
if (info->full) {
regmask_set(&ctx->regs.used_merged, (src*2)+0, false);
regmask_set(&ctx->regs.used_merged, (src*2)+1, false);
} else {
regmask_set(&ctx->regs.used_merged, src, false);
}
if (!info->r)
break;
}
} else if (info->c) {
int i, num = regidx(reg);
for (i = 0; i <= ctx->repeat; i++) {
unsigned src = num + i;
ctx->regs.max_const = MAX2(ctx->regs.max_const, src);
if (!info->r)
break;
}
unsigned max = (num + ctx->repeat + 1 + 3) / 4;
if (max > ctx->stats->constlen)
ctx->stats->constlen = max;
}
if (info->r)
reg = idxreg(regidx(info->reg) + ctx->repeatidx);
@@ -1309,12 +1496,10 @@ static const struct opc_info {
#define GETINFO(instr) (&(opcs[((instr)->opc_cat << NOPC_BITS) | instr_opc(instr, ctx->gpu_id)]))
// XXX hack.. probably should move this table somewhere common:
#include "ir3.h"
const char *ir3_instr_name(struct ir3_instruction *instr)
const char *disasm_a3xx_instr_name(opc_t opc)
{
if (opc_cat(instr->opc) == -1) return "??meta??";
return opcs[instr->opc].name;
if (opc_cat(opc) == -1) return "??meta??";
return opcs[opc].name;
}
static void print_single_instr(struct disasm_ctx *ctx, instr_t *instr)
@@ -1346,11 +1531,11 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
instr_t *instr = (instr_t *)dwords;
uint32_t opc = instr_opc(instr, ctx->gpu_id);
unsigned nop = 0;
unsigned cycles = ctx->instructions;
unsigned cycles = ctx->stats->instructions;
if (debug & PRINT_VERBOSE) {
fprintf(ctx->out, "%s%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
n, cycles++, dwords[1], dwords[0]);
if (debug & PRINT_RAW) {
fprintf(ctx->out, "%s:%d:%04d:%04d[%08xx_%08xx] ", levels[ctx->level],
instr->opc_cat, n, cycles++, dwords[1], dwords[0]);
}
/* NOTE: order flags are printed is a bit fugly.. but for now I
@@ -1359,13 +1544,16 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
*/
ctx->repeat = instr_repeat(instr);
ctx->instructions += 1 + ctx->repeat;
ctx->stats->instructions += 1 + ctx->repeat;
ctx->stats->instlen++;
if (instr->sync) {
fprintf(ctx->out, "(sy)");
ctx->stats->sy++;
}
if (instr->ss && ((instr->opc_cat <= 4) || (instr->opc_cat == 7))) {
fprintf(ctx->out, "(ss)");
ctx->stats->ss++;
}
if (instr->jmp_tgt)
fprintf(ctx->out, "(jp)");
@@ -1379,7 +1567,10 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
nop = (instr->cat2.src2_r * 2) + instr->cat2.src1_r;
else if ((instr->opc_cat == 3) && (instr->cat3.src1_r || instr->cat3.src2_r))
nop = (instr->cat3.src2_r * 2) + instr->cat3.src1_r;
ctx->instructions += nop;
ctx->stats->instructions += nop;
ctx->stats->nops += nop;
if (opc == OPC_NOP)
ctx->stats->nops += 1 + ctx->repeat;
if (nop)
fprintf(ctx->out, "(nop%d) ", nop);
@@ -1389,20 +1580,22 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
print_single_instr(ctx, instr);
fprintf(ctx->out, "\n");
process_reg_dst(ctx);
if ((instr->opc_cat <= 4) && (debug & EXPAND_REPEAT)) {
int i;
for (i = 0; i < nop; i++) {
if (debug & PRINT_VERBOSE) {
fprintf(ctx->out, "%s%04d:%04d[ ] ",
levels[ctx->level], n, cycles++);
fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
levels[ctx->level], instr->opc_cat, n, cycles++);
}
fprintf(ctx->out, "nop\n");
}
for (i = 0; i < ctx->repeat; i++) {
ctx->repeatidx = i + 1;
if (debug & PRINT_VERBOSE) {
fprintf(ctx->out, "%s%04d:%04d[ ] ",
levels[ctx->level], n, cycles++);
fprintf(ctx->out, "%s:%d:%04d:%04d[ ] ",
levels[ctx->level], instr->opc_cat, n, cycles++);
}
print_single_instr(ctx, instr);
fprintf(ctx->out, "\n");
@@ -1410,24 +1603,37 @@ static bool print_instr(struct disasm_ctx *ctx, uint32_t *dwords, int n)
ctx->repeatidx = 0;
}
return (instr->opc_cat == 0) && (opc == OPC_END);
return (instr->opc_cat == 0) &&
((opc == OPC_END) || (opc == OPC_CHSH));
}
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id)
{
struct shader_stats stats;
return disasm_a3xx_stat(dwords, sizedwords, level, out, gpu_id, &stats);
}
int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
unsigned gpu_id, struct shader_stats *stats)
{
struct disasm_ctx ctx;
int i;
int nop_count = 0;
bool has_end = false;
assert((sizedwords % 2) == 0);
ir3_assert((sizedwords % 2) == 0);
memset(&ctx, 0, sizeof(ctx));
ctx.out = out;
ctx.level = level;
ctx.gpu_id = gpu_id;
ctx.stats = stats;
memset(ctx.stats, 0, sizeof(*ctx.stats));
for (i = 0; i < sizedwords; i += 2) {
print_instr(&ctx, &dwords[i], i/2);
has_end |= print_instr(&ctx, &dwords[i], i/2);
if (!has_end)
continue;
if (dwords[i] == 0 && dwords[i + 1] == 0)
nop_count++;
else
@@ -1436,5 +1642,13 @@ int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned
break;
}
if (debug & PRINT_STATS)
print_reg_stats(&ctx);
return 0;
}
void disasm_a3xx_set_debug(enum debug_t d)
{
debug = d;
}

41
src/freedreno/ir3/instr-a3xx.h
View File

@@ -31,6 +31,22 @@
#include <stdbool.h>
#include <assert.h>
void ir3_assert_handler(const char *expr, const char *file, int line,
const char *func) __attribute__((weak)) __attribute__ ((__noreturn__));
/* A wrapper for assert() that allows overriding handling of a failed
* assert. This is needed for tools like crashdec which can want to
* attempt to disassemble memory that might not actually be valid
* instructions.
*/
#define ir3_assert(expr) do { \
if (!(expr)) { \
if (ir3_assert_handler) { \
ir3_assert_handler(#expr, __FILE__, __LINE__, __func__); \
} \
assert(expr); \
} \
} while (0)
/* size of largest OPC field of all the instruction categories: */
#define NOPC_BITS 6
@@ -249,6 +265,8 @@ typedef enum {
#define opc_cat(opc) ((int)((opc) >> NOPC_BITS))
#define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1)))
const char *disasm_a3xx_instr_name(opc_t opc);
typedef enum {
TYPE_F16 = 0,
TYPE_F32 = 1,
@@ -275,7 +293,7 @@ static inline uint32_t type_size(type_t type)
case TYPE_S8:
return 8;
default:
assert(0); /* invalid type */
ir3_assert(0); /* invalid type */
return 0;
}
}
@@ -315,6 +333,21 @@ typedef union PACKED {
int32_t idummy8 : 8;
} reg_t;
/* comp:
* 0 - x
* 1 - y
* 2 - z
* 3 - w
*/
static inline uint32_t regid(int num, int comp)
{
return (num << 2) | (comp & 0x3);
}
#define INVALID_REG regid(63, 0)
#define VALIDREG(r) ((r) != INVALID_REG)
#define CONDREG(r, val) COND(VALIDREG(r), (val))
/* special registers: */
#define REG_A0 61 /* address register */
#define REG_P0 62 /* predicate register */
@@ -979,8 +1012,8 @@ static inline bool is_cat6_legacy(instr_t *instr, unsigned gpu_id)
* in all cases. So we can use this to detect new encoding:
*/
if ((cat6->pad3 & 0x8) && (cat6->pad5 & 0x2)) {
assert(gpu_id >= 600);
assert(instr->cat6.opc == 0);
ir3_assert(gpu_id >= 600);
ir3_assert(instr->cat6.opc == 0);
return false;
}
@@ -1114,6 +1147,4 @@ static inline bool is_cat3_float(opc_t opc)
}
}
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
#endif /* INSTR_A3XX_H_ */

17
src/freedreno/ir3/ir3.h
View File

@@ -631,19 +631,6 @@ bool ir3_valid_flags(struct ir3_instruction *instr, unsigned n, unsigned flags);
set_foreach ((__instr)->uses, __entry) \
if ((__use = (void *)__entry->key))
#define MAX_ARRAYS 16
/* comp:
* 0 - x
* 1 - y
* 2 - z
* 3 - w
*/
static inline uint32_t regid(int num, int comp)
{
return (num << 2) | (comp & 0x3);
}
static inline uint32_t reg_num(struct ir3_register *reg)
{
return reg->num >> 2;
@@ -654,10 +641,6 @@ static inline uint32_t reg_comp(struct ir3_register *reg)
return reg->num & 0x3;
}
#define INVALID_REG regid(63, 0)
#define VALIDREG(r) ((r) != INVALID_REG)
#define CONDREG(r, val) COND(VALIDREG(r), (val))
static inline bool is_flow(struct ir3_instruction *instr)
{
return (opc_cat(instr->opc) == 0);

2
src/freedreno/ir3/ir3_print.c
View File

@@ -114,7 +114,7 @@ static void print_instr_name(struct ir3_instruction *instr, bool flags)
printf(".%s%s", type_name(instr->cat1.src_type),
type_name(instr->cat1.dst_type));
} else {
printf("%s", ir3_instr_name(instr));
printf("%s", disasm_a3xx_instr_name(instr->opc));
if (instr->flags & IR3_INSTR_3D)
printf(".3d");
if (instr->flags & IR3_INSTR_A)

2
src/freedreno/ir3/ir3_shader.c
View File

@@ -36,6 +36,8 @@
#include "ir3_compiler.h"
#include "ir3_nir.h"
#include "disasm.h"
int
ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
{

25
src/freedreno/ir3/regmask.h
View File

@@ -86,6 +86,31 @@ __regmask_set(regmask_t *regmask, bool half, unsigned n)
}
}
static inline void
__regmask_clear(regmask_t *regmask, bool half, unsigned n)
{
if (regmask->mergedregs) {
/* a6xx+ case, with merged register file, we track things in terms
* of half-precision registers, with a full precisions register
* using two half-precision slots:
*/
if (half) {
BITSET_CLEAR(regmask->mask, n);
} else {
n *= 2;
BITSET_CLEAR(regmask->mask, n);
BITSET_CLEAR(regmask->mask, n+1);
}
} else {
/* pre a6xx case, with separate register file for half and full
* precision:
*/
if (half)
n += MAX_REG;
BITSET_CLEAR(regmask->mask, n);
}
}
static inline void
regmask_init(regmask_t *regmask, bool mergedregs)
{

2
src/freedreno/ir3/tests/disasm.c
View File

@@ -35,7 +35,7 @@
#include <stdlib.h>
#include <string.h>
#include "util/macros.h"
#include "instr-a3xx.h"
#include "disasm.h"
#define INSTR_5XX(i, d) { .gpu_id = 540, .instr = #i, .expected = d }
#define INSTR_6XX(i, d) { .gpu_id = 630, .instr = #i, .expected = d }

2
src/freedreno/meson.build
View File

@@ -18,7 +18,7 @@
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
inc_freedreno = include_directories(['.', './registers'])
inc_freedreno = include_directories(['.', './registers', './common'])
inc_freedreno_rnn = include_directories('rnn')
subdir('common')

4
src/gallium/drivers/freedreno/a2xx/disasm-a2xx.c
View File

@@ -112,7 +112,7 @@ static void print_export_comment(uint32_t num, gl_shader_stage type)
}
break;
default:
unreachable("not reached");
assert(!"not reached");
}
/* if we had a symbol table here, we could look
* up the name of the varying..
@@ -629,7 +629,7 @@ int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage typ
return 0;
}
void disasm_set_debug(enum debug_t d)
void disasm_a2xx_set_debug(enum debug_t d)
{
debug = d;
}

43
src/gallium/drivers/freedreno/disasm.h
View File

@@ -1,43 +0,0 @@
/*
* Copyright © 2012 Rob Clark <robclark@freedesktop.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef DISASM_H_
#define DISASM_H_
#include <stdio.h>
#include <stdbool.h>
#include "compiler/shader_enums.h"
#include "util/u_debug.h"
/* bitmask of debug flags */
enum debug_t {
PRINT_RAW = 0x1, /* dump raw hexdump */
PRINT_VERBOSE = 0x2,
};
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type);
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
void disasm_set_debug(enum debug_t debug);
#endif /* DISASM_H_ */

1
src/gallium/drivers/freedreno/meson.build
View File

@@ -19,7 +19,6 @@
# SOFTWARE.
files_libfreedreno = files(
'disasm.h',
'freedreno_batch.c',
'freedreno_batch.h',
'freedreno_batch_cache.c',