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intel/vec4: Assume get_nir_dest() provides a sane write-mask

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It should be providing a write mask that is all the channels.  Drop the
one case for load_input where we stomp this for no good reason.  Also,
make ALU write-masking AND with the existing mask.  This prepares us for
the next patch where we convert to new-style registers.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
This commit is contained in:
Faith Ekstrand
2023-05-18 16:58:01 -05:00
committed by Marge Bot
parent b8209d69ff
commit f783eb9ebd
1 changed files with 1 additions and 2 deletions
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3
src/intel/compiler/brw_vec4_nir.cpp
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@@ -407,7 +407,6 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
unsigned load_offset = nir_src_as_uint(instr->src[0]);
dest = get_nir_dest(instr->dest);
dest.writemask = brw_writemask_for_size(instr->num_components);
src = src_reg(ATTR, nir_intrinsic_base(instr) + load_offset,
glsl_type::uvec4_type);
@@ -1065,7 +1064,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type |
nir_dest_bit_size(instr->dest.dest));
dst_reg dst = get_nir_dest(instr->dest.dest, dst_type);
dst.writemask = instr->dest.write_mask;
dst.writemask &= instr->dest.write_mask;
assert(!instr->dest.saturate);