nvk: Add an explicit mapping from shader stages to cbuf bindings
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27048>
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8120360358
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@@ -1881,16 +1881,25 @@ nvk_flush_descriptors(struct nvk_cmd_buffer *cmd)
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desc->root.root_desc_addr = root_desc_addr;
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memcpy(root_desc_map, &desc->root, sizeof(desc->root));
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uint32_t root_cbuf_count = 0;
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/* Find cbuf maps for the 5 cbuf groups */
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const struct nvk_cbuf_map *cbuf_maps[5] = { NULL, };
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for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
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const struct nvk_shader *shader = pipeline->base.shaders[stage];
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if (!shader || shader->code_size == 0)
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continue;
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uint32_t group = stage;
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uint32_t group = nvk_cbuf_binding_for_stage(stage);
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assert(group < ARRAY_SIZE(cbuf_maps));
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cbuf_maps[group] = &shader->cbuf_map;
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}
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for (uint32_t c = 0; c < shader->cbuf_map.cbuf_count; c++) {
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const struct nvk_cbuf *cbuf = &shader->cbuf_map.cbufs[c];
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uint32_t root_cbuf_count = 0;
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for (uint32_t group = 0; group < ARRAY_SIZE(cbuf_maps); group++) {
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if (cbuf_maps[group] == NULL)
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continue;
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for (uint32_t c = 0; c < cbuf_maps[group]->cbuf_count; c++) {
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const struct nvk_cbuf *cbuf = &cbuf_maps[group]->cbufs[c];
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/* We bind these at the very end */
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if (cbuf->type == NVK_CBUF_TYPE_ROOT_DESC) {
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@@ -1952,15 +1961,13 @@ nvk_flush_descriptors(struct nvk_cmd_buffer *cmd)
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P_NV9097_SET_CONSTANT_BUFFER_SELECTOR_B(p, root_desc_addr >> 32);
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P_NV9097_SET_CONSTANT_BUFFER_SELECTOR_C(p, root_desc_addr);
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for (gl_shader_stage stage = 0; stage < MESA_SHADER_STAGES; stage++) {
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const struct nvk_shader *shader = pipeline->base.shaders[stage];
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if (!shader || shader->code_size == 0)
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for (uint32_t group = 0; group < ARRAY_SIZE(cbuf_maps); group++) {
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if (cbuf_maps[group] == NULL)
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continue;
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uint32_t group = stage;
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for (uint32_t c = 0; c < shader->cbuf_map.cbuf_count; c++) {
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if (shader->cbuf_map.cbufs[c].type == NVK_CBUF_TYPE_ROOT_DESC) {
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for (uint32_t c = 0; c < cbuf_maps[group]->cbuf_count; c++) {
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const struct nvk_cbuf *cbuf = &cbuf_maps[group]->cbufs[c];
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if (cbuf->type == NVK_CBUF_TYPE_ROOT_DESC) {
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P_IMMD(p, NV9097, BIND_GROUP_CONSTANT_BUFFER(group), {
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.valid = VALID_TRUE,
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.shader_slot = c,
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@@ -352,7 +352,7 @@ nvk_graphics_pipeline_create(struct nvk_device *dev,
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P_MTHD(p, NVC397, SET_PIPELINE_REGISTER_COUNT(idx));
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P_NVC397_SET_PIPELINE_REGISTER_COUNT(p, idx, shader->info.num_gprs);
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P_NVC397_SET_PIPELINE_BINDING(p, idx, stage);
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P_NVC397_SET_PIPELINE_BINDING(p, idx, nvk_cbuf_binding_for_stage(stage));
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switch (stage) {
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case MESA_SHADER_VERTEX:
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@@ -27,6 +27,12 @@ struct vk_shader_module;
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#define TU102_SHADER_HEADER_SIZE (32 * 4)
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#define NVC0_MAX_SHADER_HEADER_SIZE TU102_SHADER_HEADER_SIZE
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static inline uint32_t
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nvk_cbuf_binding_for_stage(gl_shader_stage stage)
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{
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return stage;
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}
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enum ENUM_PACKED nvk_cbuf_type {
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NVK_CBUF_TYPE_INVALID = 0,
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NVK_CBUF_TYPE_ROOT_DESC,
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