intel/compiler: Use a struct for brw_compile_fs parameters
Makes calling code more explicit about what is being set, and allows take advantage of zero initialization for the ones the callsite don't care. Besides moving to the struct, two extra "ergonomic" changes were done: - Add a new shader_time boolean, so shader_time_index is ignored when unused -- this allow taking advantage of the zero initialization of unset fields. - Since we have a struct, provide space for the error_str pointer. Both iris and i965 were using it, and the extra rstrdup in case of failure shouldn't be a burden for the others. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
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@@ -1529,24 +1529,42 @@ brw_compile_clip(const struct brw_compiler *compiler,
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struct brw_vue_map *vue_map,
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unsigned *final_assembly_size);
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/**
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* Parameters for compiling a fragment shader.
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*
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* Some of these will be modified during the shader compilation.
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*/
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struct brw_compile_fs_params {
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nir_shader *nir;
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const struct brw_wm_prog_key *key;
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struct brw_wm_prog_data *prog_data;
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const struct brw_vue_map *vue_map;
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bool shader_time;
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int shader_time_index8;
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int shader_time_index16;
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int shader_time_index32;
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bool allow_spilling;
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bool use_rep_send;
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struct brw_compile_stats *stats;
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void *log_data;
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char *error_str;
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};
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/**
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* Compile a fragment shader.
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*
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* Returns the final assembly and the program's size.
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* Returns the final assembly and updates the parameters structure.
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*/
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const unsigned *
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brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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brw_compile_fs(const struct brw_compiler *compiler,
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void *mem_ctx,
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const struct brw_wm_prog_key *key,
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struct brw_wm_prog_data *prog_data,
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nir_shader *nir,
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int shader_time_index8,
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int shader_time_index16,
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int shader_time_index32,
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bool allow_spilling,
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bool use_rep_send, const struct brw_vue_map *vue_map,
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struct brw_compile_stats *stats, /**< Array of three stats */
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char **error_str);
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struct brw_compile_fs_params *params);
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/**
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* Compile a compute shader.
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@@ -9055,17 +9055,15 @@ brw_register_blocks(int reg_count)
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}
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const unsigned *
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brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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brw_compile_fs(const struct brw_compiler *compiler,
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void *mem_ctx,
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const struct brw_wm_prog_key *key,
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struct brw_wm_prog_data *prog_data,
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nir_shader *nir,
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int shader_time_index8, int shader_time_index16,
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int shader_time_index32, bool allow_spilling,
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bool use_rep_send, const struct brw_vue_map *vue_map,
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struct brw_compile_stats *stats,
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char **error_str)
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struct brw_compile_fs_params *params)
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{
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struct nir_shader *nir = params->nir;
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const struct brw_wm_prog_key *key = params->key;
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struct brw_wm_prog_data *prog_data = params->prog_data;
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bool allow_spilling = params->allow_spilling;
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prog_data->base.stage = MESA_SHADER_FRAGMENT;
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const struct gen_device_info *devinfo = compiler->devinfo;
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@@ -9076,7 +9074,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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brw_nir_lower_fs_outputs(nir);
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if (devinfo->gen < 6)
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brw_setup_vue_interpolation(vue_map, nir, prog_data);
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brw_setup_vue_interpolation(params->vue_map, nir, prog_data);
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/* From the SKL PRM, Volume 7, "Alpha Coverage":
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* "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
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@@ -9103,12 +9101,11 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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float throughput = 0;
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bool has_spilled = false;
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v8 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 8, shader_time_index8);
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v8 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 8,
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params->shader_time ? params->shader_time_index8 : -1);
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if (!v8->run_fs(allow_spilling, false /* do_rep_send */)) {
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if (error_str)
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*error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
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params->error_str = ralloc_strdup(mem_ctx, v8->fail_msg);
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delete v8;
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return NULL;
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} else if (!(INTEL_DEBUG & DEBUG_NO8)) {
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@@ -9126,20 +9123,21 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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*/
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if (devinfo->gen == 8 && prog_data->dual_src_blend &&
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!(INTEL_DEBUG & DEBUG_NO8)) {
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assert(!use_rep_send);
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assert(!params->use_rep_send);
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v8->limit_dispatch_width(8, "gen8 workaround: "
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"using SIMD8 when dual src blending.\n");
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}
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if (!has_spilled &&
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v8->max_dispatch_width >= 16 &&
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(!(INTEL_DEBUG & DEBUG_NO16) || use_rep_send)) {
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(!(INTEL_DEBUG & DEBUG_NO16) || params->use_rep_send)) {
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/* Try a SIMD16 compile */
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v16 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 16, shader_time_index16);
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v16 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 16,
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params->shader_time ? params->shader_time_index16 : -1);
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v16->import_uniforms(v8);
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if (!v16->run_fs(allow_spilling, use_rep_send)) {
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compiler->shader_perf_log(log_data,
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if (!v16->run_fs(allow_spilling, params->use_rep_send)) {
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compiler->shader_perf_log(params->log_data,
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"SIMD16 shader failed to compile: %s",
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v16->fail_msg);
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} else {
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@@ -9157,22 +9155,23 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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/* Currently, the compiler only supports SIMD32 on SNB+ */
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if (!has_spilled &&
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v8->max_dispatch_width >= 32 && !use_rep_send &&
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v8->max_dispatch_width >= 32 && !params->use_rep_send &&
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devinfo->gen >= 6 && !simd16_failed &&
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!(INTEL_DEBUG & DEBUG_NO32)) {
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/* Try a SIMD32 compile */
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v32 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 32, shader_time_index32);
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v32 = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base,
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&prog_data->base, nir, 32,
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params->shader_time ? params->shader_time_index32 : -1);
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v32->import_uniforms(v8);
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if (!v32->run_fs(allow_spilling, false)) {
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compiler->shader_perf_log(log_data,
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compiler->shader_perf_log(params->log_data,
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"SIMD32 shader failed to compile: %s",
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v32->fail_msg);
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} else {
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const performance &perf = v32->performance_analysis.require();
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if (!(INTEL_DEBUG & DEBUG_DO32) && throughput >= perf.throughput) {
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compiler->shader_perf_log(log_data, "SIMD32 shader inefficient\n");
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compiler->shader_perf_log(params->log_data, "SIMD32 shader inefficient\n");
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} else {
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simd32_cfg = v32->cfg;
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prog_data->dispatch_grf_start_reg_32 = v32->payload.num_regs;
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@@ -9183,7 +9182,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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}
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/* When the caller requests a repclear shader, they want SIMD16-only */
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if (use_rep_send)
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if (params->use_rep_send)
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simd8_cfg = NULL;
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/* Prior to Iron Lake, the PS had a single shader offset with a jump table
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@@ -9236,7 +9235,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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simd16_cfg = NULL;
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}
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fs_generator g(compiler, log_data, mem_ctx, &prog_data->base,
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fs_generator g(compiler, params->log_data, mem_ctx, &prog_data->base,
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v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT);
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if (INTEL_DEBUG & DEBUG_WM) {
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@@ -9246,6 +9245,8 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
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nir->info.name));
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}
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struct brw_compile_stats *stats = params->stats;
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if (simd8_cfg) {
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prog_data->dispatch_8 = true;
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g.generate_code(simd8_cfg, 8, v8->shader_stats,
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