OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

freedreno/afuc: Re-indent

Browse Source 
clang-format -fallback-style=none --style=file -i src/freedreno/afuc/*.[ch]

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10293>
This commit is contained in:
Rob Clark
2021-04-16 10:49:48 -07:00
committed by Marge Bot
parent b94db11708
commit f5918f750f
4 changed files with 1250 additions and 1219 deletions
Download Patch File Download Diff File Expand all files Collapse all files

254
src/freedreno/afuc/afuc.h
View File

@@ -41,154 +41,152 @@ RB.
* (ie. top two bits are '11' are encoded as 6 bits. See get_opc()
*/
typedef enum {
OPC_NOP = 0x00,
OPC_NOP = 0x00,
OPC_ADD = 0x01, /* add immediate */
OPC_ADDHI = 0x02, /* add immediate (hi 32b of 64b) */
OPC_SUB = 0x03, /* subtract immediate */
OPC_SUBHI = 0x04, /* subtract immediate (hi 32b of 64b) */
OPC_AND = 0x05, /* AND immediate */
OPC_OR = 0x06, /* OR immediate */
OPC_XOR = 0x07, /* XOR immediate */
OPC_NOT = 0x08, /* bitwise not of immed (src1 ignored) */
OPC_SHL = 0x09, /* shift-left immediate */
OPC_USHR = 0x0a, /* unsigned shift right by immediate */
OPC_ISHR = 0x0b, /* signed shift right by immediate */
OPC_ROT = 0x0c, /* rotate left (left shift with wrap-around) */
OPC_MUL8 = 0x0d, /* 8bit multiply by immediate */
OPC_MIN = 0x0e,
OPC_MAX = 0x0f,
OPC_CMP = 0x10, /* compare src to immed */
OPC_MOVI = 0x11, /* move immediate */
OPC_ADD = 0x01, /* add immediate */
OPC_ADDHI = 0x02, /* add immediate (hi 32b of 64b) */
OPC_SUB = 0x03, /* subtract immediate */
OPC_SUBHI = 0x04, /* subtract immediate (hi 32b of 64b) */
OPC_AND = 0x05, /* AND immediate */
OPC_OR = 0x06, /* OR immediate */
OPC_XOR = 0x07, /* XOR immediate */
OPC_NOT = 0x08, /* bitwise not of immed (src1 ignored) */
OPC_SHL = 0x09, /* shift-left immediate */
OPC_USHR = 0x0a, /* unsigned shift right by immediate */
OPC_ISHR = 0x0b, /* signed shift right by immediate */
OPC_ROT = 0x0c, /* rotate left (left shift with wrap-around) */
OPC_MUL8 = 0x0d, /* 8bit multiply by immediate */
OPC_MIN = 0x0e,
OPC_MAX = 0x0f,
OPC_CMP = 0x10, /* compare src to immed */
OPC_MOVI = 0x11, /* move immediate */
/* Return the most-significant bit of src2, or 0 if src2 == 0 (the
* same as if src2 == 1). src1 is ignored. Note that this overlaps
* with STORE6, so it can only be used with the two-source encoding.
*/
OPC_MSB = 0x14,
/* Return the most-significant bit of src2, or 0 if src2 == 0 (the
* same as if src2 == 1). src1 is ignored. Note that this overlaps
* with STORE6, so it can only be used with the two-source encoding.
*/
OPC_MSB = 0x14,
OPC_ALU = 0x13, /* ALU instruction with two src registers */
OPC_ALU = 0x13, /* ALU instruction with two src registers */
/* These seem something to do with setting some external state..
* doesn't seem to map *directly* to registers, but I guess that
* is where things end up. For example, this sequence in the
* CP_INDIRECT_BUFFER handler:
*
* mov $02, $data ; low 32b of IB target address
* mov $03, $data ; high 32b of IB target
* mov $04, $data ; IB size in dwords
* breq $04, 0x0, #l23 (#69, 04a2)
* and $05, $18, 0x0003
* shl $05, $05, 0x0002
* cwrite $02, [$05 + 0x0b0], 0x8
* cwrite $03, [$05 + 0x0b1], 0x8
* cwrite $04, [$05 + 0x0b2], 0x8
*
* Note that CP_IB1/2_BASE_LO/HI/BUFSZ in 0x0b1f->0xb21 (IB1) and
* 0x0b22->0x0b24 (IB2). Presumably $05 ends up w/ different value
* for RB->IB1 vs IB1->IB2.
*/
OPC_CWRITE5 = 0x15,
OPC_CREAD5 = 0x16,
/* These seem something to do with setting some external state..
* doesn't seem to map *directly* to registers, but I guess that
* is where things end up. For example, this sequence in the
* CP_INDIRECT_BUFFER handler:
*
* mov $02, $data ; low 32b of IB target address
* mov $03, $data ; high 32b of IB target
* mov $04, $data ; IB size in dwords
* breq $04, 0x0, #l23 (#69, 04a2)
* and $05, $18, 0x0003
* shl $05, $05, 0x0002
* cwrite $02, [$05 + 0x0b0], 0x8
* cwrite $03, [$05 + 0x0b1], 0x8
* cwrite $04, [$05 + 0x0b2], 0x8
*
* Note that CP_IB1/2_BASE_LO/HI/BUFSZ in 0x0b1f->0xb21 (IB1) and
* 0x0b22->0x0b24 (IB2). Presumably $05 ends up w/ different value
* for RB->IB1 vs IB1->IB2.
*/
OPC_CWRITE5 = 0x15,
OPC_CREAD5 = 0x16,
/* A6xx shuffled around the cwrite/cread opcodes and added new opcodes
* that let you read/write directly to memory (and bypass the IOMMU?).
*/
OPC_STORE6 = 0x14,
OPC_CWRITE6 = 0x15,
OPC_LOAD6 = 0x16,
OPC_CREAD6 = 0x17,
/* A6xx shuffled around the cwrite/cread opcodes and added new opcodes
* that let you read/write directly to memory (and bypass the IOMMU?).
*/
OPC_STORE6 = 0x14,
OPC_CWRITE6 = 0x15,
OPC_LOAD6 = 0x16,
OPC_CREAD6 = 0x17,
OPC_BRNEI = 0x30, /* relative branch (if $src != immed) */
OPC_BREQI = 0x31, /* relative branch (if $src == immed) */
OPC_BRNEB = 0x32, /* relative branch (if bit not set) */
OPC_BREQB = 0x33, /* relative branch (if bit is set) */
OPC_RET = 0x34, /* return */
OPC_CALL = 0x35, /* "function" call */
OPC_WIN = 0x36, /* wait for input (ie. wait for WPTR to advance) */
OPC_PREEMPTLEAVE6 = 0x38, /* try to leave preemption */
OPC_SETSECURE = 0x3b, /* switch secure mode on/off */
OPC_BRNEI = 0x30, /* relative branch (if $src != immed) */
OPC_BREQI = 0x31, /* relative branch (if $src == immed) */
OPC_BRNEB = 0x32, /* relative branch (if bit not set) */
OPC_BREQB = 0x33, /* relative branch (if bit is set) */
OPC_RET = 0x34, /* return */
OPC_CALL = 0x35, /* "function" call */
OPC_WIN = 0x36, /* wait for input (ie. wait for WPTR to advance) */
OPC_PREEMPTLEAVE6 = 0x38, /* try to leave preemption */
OPC_SETSECURE = 0x3b, /* switch secure mode on/off */
} afuc_opc;
typedef union PACKED {
/* addi, subi, andi, ori, xori, etc: */
struct PACKED {
uint32_t uimm : 16;
uint32_t dst : 5;
uint32_t src : 5;
uint32_t hdr : 6;
} alui;
struct PACKED {
uint32_t uimm : 16;
uint32_t dst : 5;
uint32_t shift : 5;
uint32_t hdr : 6;
} movi;
struct PACKED {
uint32_t alu : 5;
uint32_t pad : 4;
uint32_t xmov : 2; /* execute eXtra mov's based on $rem */
uint32_t dst : 5;
uint32_t src2 : 5;
uint32_t src1 : 5;
uint32_t hdr : 6;
} alu;
struct PACKED {
uint32_t uimm : 12;
uint32_t flags : 4;
uint32_t src1 : 5; /* dst (cread) or src (cwrite) register */
uint32_t src2 : 5; /* read or write address is src2+uimm */
uint32_t hdr : 6;
} control;
struct PACKED {
int32_t ioff : 16; /* relative offset */
uint32_t bit_or_imm : 5;
uint32_t src : 5;
uint32_t hdr : 6;
} br;
struct PACKED {
uint32_t uoff : 26; /* absolute (unsigned) offset */
uint32_t hdr : 6;
} call;
struct PACKED {
uint32_t pad : 25;
uint32_t interrupt : 1; /* return from ctxt-switch interrupt handler */
uint32_t hdr : 6;
} ret;
struct PACKED {
uint32_t pad : 26;
uint32_t hdr : 6;
} waitin;
struct PACKED {
uint32_t pad : 26;
uint32_t opc_r : 6;
};
/* addi, subi, andi, ori, xori, etc: */
struct PACKED {
uint32_t uimm : 16;
uint32_t dst : 5;
uint32_t src : 5;
uint32_t hdr : 6;
} alui;
struct PACKED {
uint32_t uimm : 16;
uint32_t dst : 5;
uint32_t shift : 5;
uint32_t hdr : 6;
} movi;
struct PACKED {
uint32_t alu : 5;
uint32_t pad : 4;
uint32_t xmov : 2; /* execute eXtra mov's based on $rem */
uint32_t dst : 5;
uint32_t src2 : 5;
uint32_t src1 : 5;
uint32_t hdr : 6;
} alu;
struct PACKED {
uint32_t uimm : 12;
uint32_t flags : 4;
uint32_t src1 : 5; /* dst (cread) or src (cwrite) register */
uint32_t src2 : 5; /* read or write address is src2+uimm */
uint32_t hdr : 6;
} control;
struct PACKED {
int32_t ioff : 16; /* relative offset */
uint32_t bit_or_imm : 5;
uint32_t src : 5;
uint32_t hdr : 6;
} br;
struct PACKED {
uint32_t uoff : 26; /* absolute (unsigned) offset */
uint32_t hdr : 6;
} call;
struct PACKED {
uint32_t pad : 25;
uint32_t interrupt : 1; /* return from ctxt-switch interrupt handler */
uint32_t hdr : 6;
} ret;
struct PACKED {
uint32_t pad : 26;
uint32_t hdr : 6;
} waitin;
struct PACKED {
uint32_t pad : 26;
uint32_t opc_r : 6;
};
} afuc_instr;
static inline void
afuc_get_opc(afuc_instr *ai, afuc_opc *opc, bool *rep)
{
if (ai->opc_r < 0x30) {
*opc = ai->opc_r >> 1;
*rep = ai->opc_r & 0x1;
} else {
*opc = ai->opc_r;
*rep = false;
}
if (ai->opc_r < 0x30) {
*opc = ai->opc_r >> 1;
*rep = ai->opc_r & 0x1;
} else {
*opc = ai->opc_r;
*rep = false;
}
}
static inline void
afuc_set_opc(afuc_instr *ai, afuc_opc opc, bool rep)
{
if (opc < 0x30) {
ai->opc_r = opc << 1;
ai->opc_r |= !!rep;
} else {
ai->opc_r = opc;
}
if (opc < 0x30) {
ai->opc_r = opc << 1;
ai->opc_r |= !!rep;
} else {
ai->opc_r = opc;
}
}
#endif /* _AFUC_H_ */

731
src/freedreno/afuc/asm.c
View File

@@ -21,34 +21,32 @@
* SOFTWARE.
*/
#include <err.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <err.h>
#include <fcntl.h>
#include <getopt.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "util/macros.h"
#include "afuc.h"
#include "asm.h"
#include "parser.h"
#include "rnn.h"
#include "rnndec.h"
#include "parser.h"
#include "asm.h"
int gpuver;
static struct rnndeccontext *ctx;
static struct rnndb *db;
static struct rnndomain *control_regs;
struct rnndomain *dom[2];
/* bit lame to hard-code max but fw sizes are small */
static struct asm_instruction instructions[0x2000];
static unsigned num_instructions;
@@ -56,410 +54,437 @@ static unsigned num_instructions;
static struct asm_label labels[0x512];
static unsigned num_labels;
struct asm_instruction *next_instr(int tok)
struct asm_instruction *
next_instr(int tok)
{
struct asm_instruction *ai = &instructions[num_instructions++];
assert(num_instructions < ARRAY_SIZE(instructions));
ai->tok = tok;
return ai;
struct asm_instruction *ai = &instructions[num_instructions++];
assert(num_instructions < ARRAY_SIZE(instructions));
ai->tok = tok;
return ai;
}
void decl_label(const char *str)
void
decl_label(const char *str)
{
struct asm_label *label = &labels[num_labels++];
struct asm_label *label = &labels[num_labels++];
assert(num_labels < ARRAY_SIZE(labels));
assert(num_labels < ARRAY_SIZE(labels));
label->offset = num_instructions;
label->label = str;
label->offset = num_instructions;
label->label = str;
}
static int resolve_label(const char *str)
static int
resolve_label(const char *str)
{
int i;
int i;
for (i = 0; i < num_labels; i++) {
struct asm_label *label = &labels[i];
for (i = 0; i < num_labels; i++) {
struct asm_label *label = &labels[i];
if (!strcmp(str, label->label)) {
return label->offset;
}
}
if (!strcmp(str, label->label)) {
return label->offset;
}
}
fprintf(stderr, "Undeclared label: %s\n", str);
exit(2);
fprintf(stderr, "Undeclared label: %s\n", str);
exit(2);
}
static afuc_opc tok2alu(int tok)
static afuc_opc
tok2alu(int tok)
{
switch (tok) {
case T_OP_ADD: return OPC_ADD;
case T_OP_ADDHI: return OPC_ADDHI;
case T_OP_SUB: return OPC_SUB;
case T_OP_SUBHI: return OPC_SUBHI;
case T_OP_AND: return OPC_AND;
case T_OP_OR: return OPC_OR;
case T_OP_XOR: return OPC_XOR;
case T_OP_NOT: return OPC_NOT;
case T_OP_SHL: return OPC_SHL;
case T_OP_USHR: return OPC_USHR;
case T_OP_ISHR: return OPC_ISHR;
case T_OP_ROT: return OPC_ROT;
case T_OP_MUL8: return OPC_MUL8;
case T_OP_MIN: return OPC_MIN;
case T_OP_MAX: return OPC_MAX;
case T_OP_CMP: return OPC_CMP;
case T_OP_MSB: return OPC_MSB;
default:
assert(0);
return -1;
}
switch (tok) {
case T_OP_ADD:
return OPC_ADD;
case T_OP_ADDHI:
return OPC_ADDHI;
case T_OP_SUB:
return OPC_SUB;
case T_OP_SUBHI:
return OPC_SUBHI;
case T_OP_AND:
return OPC_AND;
case T_OP_OR:
return OPC_OR;
case T_OP_XOR:
return OPC_XOR;
case T_OP_NOT:
return OPC_NOT;
case T_OP_SHL:
return OPC_SHL;
case T_OP_USHR:
return OPC_USHR;
case T_OP_ISHR:
return OPC_ISHR;
case T_OP_ROT:
return OPC_ROT;
case T_OP_MUL8:
return OPC_MUL8;
case T_OP_MIN:
return OPC_MIN;
case T_OP_MAX:
return OPC_MAX;
case T_OP_CMP:
return OPC_CMP;
case T_OP_MSB:
return OPC_MSB;
default:
assert(0);
return -1;
}
}
static void emit_instructions(int outfd)
static void
emit_instructions(int outfd)
{
int i;
int i;
/* there is an extra 0x00000000 which kernel strips off.. we could
* perhaps use it for versioning.
*/
i = 0;
write(outfd, &i, 4);
/* there is an extra 0x00000000 which kernel strips off.. we could
* perhaps use it for versioning.
*/
i = 0;
write(outfd, &i, 4);
for (i = 0; i < num_instructions; i++) {
struct asm_instruction *ai = &instructions[i];
afuc_instr instr = {0};
afuc_opc opc;
for (i = 0; i < num_instructions; i++) {
struct asm_instruction *ai = &instructions[i];
afuc_instr instr = {0};
afuc_opc opc;
/* special case, 2nd dword is patched up w/ # of instructions
* (ie. offset of jmptbl)
*/
if (i == 1) {
assert(ai->is_literal);
ai->literal &= ~0xffff;
ai->literal |= num_instructions;
}
/* special case, 2nd dword is patched up w/ # of instructions
* (ie. offset of jmptbl)
*/
if (i == 1) {
assert(ai->is_literal);
ai->literal &= ~0xffff;
ai->literal |= num_instructions;
}
if (ai->is_literal) {
write(outfd, &ai->literal, 4);
continue;
}
if (ai->is_literal) {
write(outfd, &ai->literal, 4);
continue;
}
switch (ai->tok) {
case T_OP_NOP:
opc = OPC_NOP;
if (gpuver >= 6)
instr.pad = 0x1000000;
break;
case T_OP_ADD:
case T_OP_ADDHI:
case T_OP_SUB:
case T_OP_SUBHI:
case T_OP_AND:
case T_OP_OR:
case T_OP_XOR:
case T_OP_NOT:
case T_OP_SHL:
case T_OP_USHR:
case T_OP_ISHR:
case T_OP_ROT:
case T_OP_MUL8:
case T_OP_MIN:
case T_OP_MAX:
case T_OP_CMP:
case T_OP_MSB:
if (ai->has_immed) {
/* MSB overlaps with STORE */
assert(ai->tok != T_OP_MSB);
if (ai->xmov) {
fprintf(stderr, "ALU instruction cannot have immediate and xmov\n");
exit(1);
}
opc = tok2alu(ai->tok);
instr.alui.dst = ai->dst;
instr.alui.src = ai->src1;
instr.alui.uimm = ai->immed;
} else {
opc = OPC_ALU;
instr.alu.dst = ai->dst;
instr.alu.src1 = ai->src1;
instr.alu.src2 = ai->src2;
instr.alu.xmov = ai->xmov;
instr.alu.alu = tok2alu(ai->tok);
}
break;
case T_OP_MOV:
/* move can either be encoded as movi (ie. move w/ immed) or
* an alu instruction
*/
if ((ai->has_immed || ai->label) && ai->xmov) {
fprintf(stderr, "ALU instruction cannot have immediate and xmov\n");
exit(1);
}
if (ai->has_immed) {
opc = OPC_MOVI;
instr.movi.dst = ai->dst;
instr.movi.uimm = ai->immed;
instr.movi.shift = ai->shift;
} else if (ai->label) {
/* mov w/ a label is just an alias for an immediate, this
* is useful to load the address of a constant table into
* a register:
*/
opc = OPC_MOVI;
instr.movi.dst = ai->dst;
instr.movi.uimm = resolve_label(ai->label);
instr.movi.shift = ai->shift;
} else {
/* encode as: or $dst, $00, $src */
opc = OPC_ALU;
instr.alu.dst = ai->dst;
instr.alu.src1 = 0x00; /* $00 reads-back 0 */
instr.alu.src2 = ai->src1;
instr.alu.xmov = ai->xmov;
instr.alu.alu = OPC_OR;
}
break;
case T_OP_CWRITE:
case T_OP_CREAD:
case T_OP_STORE:
case T_OP_LOAD:
if (gpuver >= 6) {
if (ai->tok == T_OP_CWRITE) {
opc = OPC_CWRITE6;
} else if (ai->tok == T_OP_CREAD) {
opc = OPC_CREAD6;
} else if (ai->tok == T_OP_STORE) {
opc = OPC_STORE6;
} else if (ai->tok == T_OP_LOAD) {
opc = OPC_LOAD6;
}
} else {
if (ai->tok == T_OP_CWRITE) {
opc = OPC_CWRITE5;
} else if (ai->tok == T_OP_CREAD) {
opc = OPC_CREAD5;
} else if (ai->tok == T_OP_STORE ||
ai->tok == T_OP_LOAD) {
fprintf(stderr, "load and store do not exist on a5xx\n");
exit(1);
}
}
instr.control.src1 = ai->src1;
instr.control.src2 = ai->src2;
instr.control.flags = ai->bit;
instr.control.uimm = ai->immed;
break;
case T_OP_BRNE:
case T_OP_BREQ:
if (ai->has_immed) {
opc = (ai->tok == T_OP_BRNE) ? OPC_BRNEI : OPC_BREQI;
instr.br.bit_or_imm = ai->immed;
} else {
opc = (ai->tok == T_OP_BRNE) ? OPC_BRNEB : OPC_BREQB;
instr.br.bit_or_imm = ai->bit;
}
instr.br.src = ai->src1;
instr.br.ioff = resolve_label(ai->label) - i;
break;
case T_OP_RET:
opc = OPC_RET;
break;
case T_OP_IRET:
opc = OPC_RET;
instr.ret.interrupt = 1;
break;
case T_OP_CALL:
opc = OPC_CALL;
instr.call.uoff = resolve_label(ai->label);
break;
case T_OP_PREEMPTLEAVE:
opc = OPC_PREEMPTLEAVE6;
instr.call.uoff = resolve_label(ai->label);
break;
case T_OP_SETSECURE:
opc = OPC_SETSECURE;
if (resolve_label(ai->label) != i + 3) {
fprintf(stderr, "jump label %s is incorrect for setsecure\n", ai->label);
exit(1);
}
if (ai->src1 != 0x2) {
fprintf(stderr, "source for setsecure must be $02\n");
exit(1);
}
break;
case T_OP_JUMP:
/* encode jump as: brne $00, b0, #label */
opc = OPC_BRNEB;
instr.br.bit_or_imm = 0;
instr.br.src = 0x00; /* $00 reads-back 0.. compare to 0 */
instr.br.ioff = resolve_label(ai->label) - i;
break;
case T_OP_WAITIN:
opc = OPC_WIN;
break;
default:
unreachable("");
}
switch (ai->tok) {
case T_OP_NOP:
opc = OPC_NOP;
if (gpuver >= 6)
instr.pad = 0x1000000;
break;
case T_OP_ADD:
case T_OP_ADDHI:
case T_OP_SUB:
case T_OP_SUBHI:
case T_OP_AND:
case T_OP_OR:
case T_OP_XOR:
case T_OP_NOT:
case T_OP_SHL:
case T_OP_USHR:
case T_OP_ISHR:
case T_OP_ROT:
case T_OP_MUL8:
case T_OP_MIN:
case T_OP_MAX:
case T_OP_CMP:
case T_OP_MSB:
if (ai->has_immed) {
/* MSB overlaps with STORE */
assert(ai->tok != T_OP_MSB);
if (ai->xmov) {
fprintf(stderr,
"ALU instruction cannot have immediate and xmov\n");
exit(1);
}
opc = tok2alu(ai->tok);
instr.alui.dst = ai->dst;
instr.alui.src = ai->src1;
instr.alui.uimm = ai->immed;
} else {
opc = OPC_ALU;
instr.alu.dst = ai->dst;
instr.alu.src1 = ai->src1;
instr.alu.src2 = ai->src2;
instr.alu.xmov = ai->xmov;
instr.alu.alu = tok2alu(ai->tok);
}
break;
case T_OP_MOV:
/* move can either be encoded as movi (ie. move w/ immed) or
* an alu instruction
*/
if ((ai->has_immed || ai->label) && ai->xmov) {
fprintf(stderr, "ALU instruction cannot have immediate and xmov\n");
exit(1);
}
if (ai->has_immed) {
opc = OPC_MOVI;
instr.movi.dst = ai->dst;
instr.movi.uimm = ai->immed;
instr.movi.shift = ai->shift;
} else if (ai->label) {
/* mov w/ a label is just an alias for an immediate, this
* is useful to load the address of a constant table into
* a register:
*/
opc = OPC_MOVI;
instr.movi.dst = ai->dst;
instr.movi.uimm = resolve_label(ai->label);
instr.movi.shift = ai->shift;
} else {
/* encode as: or $dst, $00, $src */
opc = OPC_ALU;
instr.alu.dst = ai->dst;
instr.alu.src1 = 0x00; /* $00 reads-back 0 */
instr.alu.src2 = ai->src1;
instr.alu.xmov = ai->xmov;
instr.alu.alu = OPC_OR;
}
break;
case T_OP_CWRITE:
case T_OP_CREAD:
case T_OP_STORE:
case T_OP_LOAD:
if (gpuver >= 6) {
if (ai->tok == T_OP_CWRITE) {
opc = OPC_CWRITE6;
} else if (ai->tok == T_OP_CREAD) {
opc = OPC_CREAD6;
} else if (ai->tok == T_OP_STORE) {
opc = OPC_STORE6;
} else if (ai->tok == T_OP_LOAD) {
opc = OPC_LOAD6;
}
} else {
if (ai->tok == T_OP_CWRITE) {
opc = OPC_CWRITE5;
} else if (ai->tok == T_OP_CREAD) {
opc = OPC_CREAD5;
} else if (ai->tok == T_OP_STORE || ai->tok == T_OP_LOAD) {
fprintf(stderr, "load and store do not exist on a5xx\n");
exit(1);
}
}
instr.control.src1 = ai->src1;
instr.control.src2 = ai->src2;
instr.control.flags = ai->bit;
instr.control.uimm = ai->immed;
break;
case T_OP_BRNE:
case T_OP_BREQ:
if (ai->has_immed) {
opc = (ai->tok == T_OP_BRNE) ? OPC_BRNEI : OPC_BREQI;
instr.br.bit_or_imm = ai->immed;
} else {
opc = (ai->tok == T_OP_BRNE) ? OPC_BRNEB : OPC_BREQB;
instr.br.bit_or_imm = ai->bit;
}
instr.br.src = ai->src1;
instr.br.ioff = resolve_label(ai->label) - i;
break;
case T_OP_RET:
opc = OPC_RET;
break;
case T_OP_IRET:
opc = OPC_RET;
instr.ret.interrupt = 1;
break;
case T_OP_CALL:
opc = OPC_CALL;
instr.call.uoff = resolve_label(ai->label);
break;
case T_OP_PREEMPTLEAVE:
opc = OPC_PREEMPTLEAVE6;
instr.call.uoff = resolve_label(ai->label);
break;
case T_OP_SETSECURE:
opc = OPC_SETSECURE;
if (resolve_label(ai->label) != i + 3) {
fprintf(stderr, "jump label %s is incorrect for setsecure\n",
ai->label);
exit(1);
}
if (ai->src1 != 0x2) {
fprintf(stderr, "source for setsecure must be $02\n");
exit(1);
}
break;
case T_OP_JUMP:
/* encode jump as: brne $00, b0, #label */
opc = OPC_BRNEB;
instr.br.bit_or_imm = 0;
instr.br.src = 0x00; /* $00 reads-back 0.. compare to 0 */
instr.br.ioff = resolve_label(ai->label) - i;
break;
case T_OP_WAITIN:
opc = OPC_WIN;
break;
default:
unreachable("");
}
afuc_set_opc(&instr, opc, ai->rep);
write(outfd, &instr, 4);
}
afuc_set_opc(&instr, opc, ai->rep);
write(outfd, &instr, 4);
}
}
static int find_enum_val(struct rnnenum *en, const char *name)
static int
find_enum_val(struct rnnenum *en, const char *name)
{
int i;
int i;
for (i = 0; i < en->valsnum; i++)
if (en->vals[i]->valvalid && !strcmp(name, en->vals[i]->name))
return en->vals[i]->value;
for (i = 0; i < en->valsnum; i++)
if (en->vals[i]->valvalid && !strcmp(name, en->vals[i]->name))
return en->vals[i]->value;
return -1;
return -1;
}
static int find_reg(struct rnndomain *dom, const char *name)
static int
find_reg(struct rnndomain *dom, const char *name)
{
int i;
int i;
for (i = 0; i < dom->subelemsnum; i++)
if (!strcmp(name, dom->subelems[i]->name))
return dom->subelems[i]->offset;
for (i = 0; i < dom->subelemsnum; i++)
if (!strcmp(name, dom->subelems[i]->name))
return dom->subelems[i]->offset;
return -1;
return -1;
}
unsigned parse_control_reg(const char *name)
unsigned
parse_control_reg(const char *name)
{
/* skip leading "@" */
int val = find_reg(control_regs, name + 1);
if (val < 0) {
printf("invalid control reg: %s\n", name);
exit(2);
}
return (unsigned)val;
/* skip leading "@" */
int val = find_reg(control_regs, name + 1);
if (val < 0) {
printf("invalid control reg: %s\n", name);
exit(2);
}
return (unsigned)val;
}
static void emit_jumptable(int outfd)
static void
emit_jumptable(int outfd)
{
struct rnnenum *en = rnn_findenum(ctx->db, "adreno_pm4_type3_packets");
uint32_t jmptable[0x80] = {0};
int i;
struct rnnenum *en = rnn_findenum(ctx->db, "adreno_pm4_type3_packets");
uint32_t jmptable[0x80] = {0};
int i;
for (i = 0; i < num_labels; i++) {
struct asm_label *label = &labels[i];
int id = find_enum_val(en, label->label);
for (i = 0; i < num_labels; i++) {
struct asm_label *label = &labels[i];
int id = find_enum_val(en, label->label);
/* if it doesn't match a known PM4 packet-id, try to match UNKN%d: */
if (id < 0) {
if (sscanf(label->label, "UNKN%d", &id) != 1) {
/* if still not found, must not belong in jump-table: */
continue;
}
}
/* if it doesn't match a known PM4 packet-id, try to match UNKN%d: */
if (id < 0) {
if (sscanf(label->label, "UNKN%d", &id) != 1) {
/* if still not found, must not belong in jump-table: */
continue;
}
}
jmptable[id] = label->offset;
}
jmptable[id] = label->offset;
}
write(outfd, jmptable, sizeof(jmptable));
write(outfd, jmptable, sizeof(jmptable));
}
static void usage(void)
static void
usage(void)
{
fprintf(stderr, "Usage:\n"
"\tasm [-g GPUVER] filename.asm filename.fw\n"
"\t\t-g - specify GPU version (5, etc)\n"
);
exit(2);
fprintf(stderr, "Usage:\n"
"\tasm [-g GPUVER] filename.asm filename.fw\n"
"\t\t-g - specify GPU version (5, etc)\n");
exit(2);
}
int main(int argc, char **argv)
int
main(int argc, char **argv)
{
FILE *in;
char *file, *outfile, *name, *control_reg_name;
int c, ret, outfd;
FILE *in;
char *file, *outfile, *name, *control_reg_name;
int c, ret, outfd;
/* Argument parsing: */
while ((c = getopt (argc, argv, "g:")) != -1) {
switch (c) {
case 'g':
gpuver = atoi(optarg);
break;
default:
usage();
}
}
/* Argument parsing: */
while ((c = getopt(argc, argv, "g:")) != -1) {
switch (c) {
case 'g':
gpuver = atoi(optarg);
break;
default:
usage();
}
}
if (optind >= (argc + 1)) {
fprintf(stderr, "no file specified!\n");
usage();
}
if (optind >= (argc + 1)) {
fprintf(stderr, "no file specified!\n");
usage();
}
file = argv[optind];
outfile = argv[optind + 1];
file = argv[optind];
outfile = argv[optind + 1];
outfd = open(outfile, O_WRONLY | O_CREAT | O_TRUNC, 0644);
if (outfd < 0) {
fprintf(stderr, "could not open \"%s\"\n", outfile);
usage();
}
outfd = open(outfile, O_WRONLY | O_CREAT | O_TRUNC, 0644);
if (outfd < 0) {
fprintf(stderr, "could not open \"%s\"\n", outfile);
usage();
}
in = fopen(file, "r");
if (!in) {
fprintf(stderr, "could not open \"%s\"\n", file);
usage();
}
in = fopen(file, "r");
if (!in) {
fprintf(stderr, "could not open \"%s\"\n", file);
usage();
}
yyset_in(in);
yyset_in(in);
/* if gpu version not specified, infer from filename: */
if (!gpuver) {
if (strstr(file, "a5")) {
gpuver = 5;
} else if (strstr(file, "a6")) {
gpuver = 6;
}
}
/* if gpu version not specified, infer from filename: */
if (!gpuver) {
if (strstr(file, "a5")) {
gpuver = 5;
} else if (strstr(file, "a6")) {
gpuver = 6;
}
}
switch (gpuver) {
case 6:
name = "A6XX";
control_reg_name = "A6XX_CONTROL_REG";
break;
case 5:
name = "A5XX";
control_reg_name = "A5XX_CONTROL_REG";
break;
default:
fprintf(stderr, "unknown GPU version!\n");
usage();
}
switch (gpuver) {
case 6:
name = "A6XX";
control_reg_name = "A6XX_CONTROL_REG";
break;
case 5:
name = "A5XX";
control_reg_name = "A5XX_CONTROL_REG";
break;
default:
fprintf(stderr, "unknown GPU version!\n");
usage();
}
rnn_init();
db = rnn_newdb();
rnn_init();
db = rnn_newdb();
ctx = rnndec_newcontext(db);
ctx = rnndec_newcontext(db);
rnn_parsefile(db, "adreno.xml");
rnn_prepdb(db);
if (db->estatus)
errx(db->estatus, "failed to parse register database");
dom[0] = rnn_finddomain(db, name);
dom[1] = rnn_finddomain(db, "AXXX");
control_regs = rnn_finddomain(db, control_reg_name);
rnn_parsefile(db, "adreno.xml");
rnn_prepdb(db);
if (db->estatus)
errx(db->estatus, "failed to parse register database");
dom[0] = rnn_finddomain(db, name);
dom[1] = rnn_finddomain(db, "AXXX");
control_regs = rnn_finddomain(db, control_reg_name);
ret = yyparse();
if (ret) {
fprintf(stderr, "parse failed: %d\n", ret);
return ret;
}
ret = yyparse();
if (ret) {
fprintf(stderr, "parse failed: %d\n", ret);
return ret;
}
emit_instructions(outfd);
emit_jumptable(outfd);
emit_instructions(outfd);
emit_jumptable(outfd);
close(outfd);
close(outfd);
return 0;
return 0;
}

96
src/freedreno/afuc/asm.h
View File

@@ -24,8 +24,8 @@
#ifndef _ASM_H_
#define _ASM_H_
#include <stdint.h>
#include <stdbool.h>
#include <stdint.h>
#include "afuc.h"
extern int gpuver;
@@ -37,78 +37,77 @@ extern int gpuver;
* about the different encodings for 2src regs vs 1src+immed, or mnemonics
*/
struct asm_instruction {
int tok;
int dst;
int src1;
int src2;
int immed;
int shift;
int bit;
int xmov;
uint32_t literal;
const char *label;
int tok;
int dst;
int src1;
int src2;
int immed;
int shift;
int bit;
int xmov;
uint32_t literal;
const char *label;
bool has_immed : 1;
bool has_shift : 1;
bool has_bit : 1;
bool is_literal : 1;
bool rep : 1;
bool has_immed : 1;
bool has_shift : 1;
bool has_bit : 1;
bool is_literal : 1;
bool rep : 1;
};
struct asm_label {
unsigned offset;
const char *label;
unsigned offset;
const char *label;
};
struct asm_instruction *next_instr(int tok);
void decl_label(const char *str);
static inline uint32_t
parse_reg(const char *str)
{
char *retstr;
long int ret;
char *retstr;
long int ret;
if (!strcmp(str, "$rem"))
return 0x1c;
else if (!strcmp(str, "$addr"))
return 0x1d;
else if (!strcmp(str, "$addr2"))
return 0x1e;
else if (!strcmp(str, "$data"))
return 0x1f;
if (!strcmp(str, "$rem"))
return 0x1c;
else if (!strcmp(str, "$addr"))
return 0x1d;
else if (!strcmp(str, "$addr2"))
return 0x1e;
else if (!strcmp(str, "$data"))
return 0x1f;
ret = strtol(str + 1, &retstr, 16);
ret = strtol(str + 1, &retstr, 16);
if (*retstr != '\0') {
printf("invalid register: %s\n", str);
exit(2);
}
if (*retstr != '\0') {
printf("invalid register: %s\n", str);
exit(2);
}
return ret;
return ret;
}
static inline uint32_t
parse_literal(const char *str)
{
char *retstr;
long int ret;
char *retstr;
long int ret;
ret = strtol(str + 1, &retstr, 16);
ret = strtol(str + 1, &retstr, 16);
if (*retstr != ']') {
printf("invalid literal: %s\n", str);
exit(2);
}
if (*retstr != ']') {
printf("invalid literal: %s\n", str);
exit(2);
}
return ret;
return ret;
}
static inline uint32_t
parse_bit(const char *str)
{
return strtol(str + 1, NULL, 10);
return strtol(str + 1, NULL, 10);
}
unsigned parse_control_reg(const char *name);
@@ -117,12 +116,11 @@ unsigned parse_control_reg(const char *name);
static inline const char *
parse_label_decl(const char *str)
{
char *s = strdup(str);
s[strlen(s) - 1] = '\0';
return s;
char *s = strdup(str);
s[strlen(s) - 1] = '\0';
return s;
}
void yyset_in (FILE * _in_str );
void yyset_in(FILE *_in_str);
#endif /* _ASM_H_ */

1388
src/freedreno/afuc/disasm.c
View File

File diff suppressed because it is too large Load Diff