tu: enable shaderInt8 support
Enable the shaderInt8 Vulkan feature for Turnip. As final necessary changes, an assert for nir_op_imul is tweaked to also allow 8-bit multiplication, and nir_op_bcsel's conversion of the conditional value from 8 to 32 bits is applied through masking, like in the general conversion case. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10675 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29875>
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@@ -758,7 +758,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
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}
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break;
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case nir_op_imul:
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compile_assert(ctx, alu->def.bit_size == 16);
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compile_assert(ctx, alu->def.bit_size == 8 || alu->def.bit_size == 16);
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dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
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break;
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case nir_op_imul24:
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@@ -841,7 +841,15 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
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cond = prev_entry->data;
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} else {
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if (is_half(cond)) {
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cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
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if (bs[0] == 8) {
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/* Zero-extension of an 8-bit value has to be done through masking,
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* as in create_cov.
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*/
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struct ir3_instruction *mask = create_immed_typed(b, 0xff, TYPE_U8);
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cond = ir3_AND_B(b, cond, 0, mask, 0);
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} else {
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cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
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}
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} else {
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cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
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}
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@@ -390,7 +390,7 @@ tu_get_features(struct tu_physical_device *pdevice,
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features->shaderBufferInt64Atomics = false;
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features->shaderSharedInt64Atomics = false;
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features->shaderFloat16 = true;
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features->shaderInt8 = false;
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features->shaderInt8 = true;
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features->descriptorIndexing = true;
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features->shaderInputAttachmentArrayDynamicIndexing = false;
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