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freedreno/ir3: Get reg_size_vec4 from fd_dev_info

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Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11790>
This commit is contained in:
Rob Clark
2021-07-08 10:02:19 -07:00
committed by Marge Bot
parent 4335f47f41
commit f4cfb5a61e
3 changed files with 8 additions and 7 deletions
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2
src/freedreno/common/freedreno_dev_info.h
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@@ -57,6 +57,8 @@ struct fd_dev_info {
/* Information for private memory calculations */
uint32_t fibers_per_sp;
uint32_t reg_size_vec4;
/* Whether the PC_MULTIVIEW_MASK register exists. */
bool supports_multiview_mask;

3
src/freedreno/common/freedreno_devices.py
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@@ -174,12 +174,14 @@ add_gpus([
# a615, a618, a630:
a6xx_gen1 = dict(
fibers_per_sp = 128 * 16,
reg_size_vec4 = 96,
ccu_cntl_gmem_unk2 = True,
)
# a640, a680:
a6xx_gen2 = dict(
fibers_per_sp = 128 * 4 * 16,
reg_size_vec4 = 96,
supports_multiview_mask = True,
has_z24uint_s8uint = True,
)
@@ -187,6 +189,7 @@ a6xx_gen2 = dict(
# a650:
a6xx_gen3 = dict(
fibers_per_sp = 128 * 2 * 16,
reg_size_vec4 = 64,
supports_multiview_mask = True,
has_z24uint_s8uint = True,
tess_use_shared = True,

10
src/freedreno/ir3/ir3_compiler.c
View File

@@ -136,13 +136,9 @@ ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id,
compiler->max_const_safe = 256;
}
if (compiler->gpu_id == 650) {
/* This changed mid-generation for a650, so that using r32.x and above
* requires using the smallest threadsize.
*/
compiler->reg_size_vec4 = 64;
} else if (compiler->gpu_id >= 600) {
compiler->reg_size_vec4 = 96;
if (compiler->gpu_id >= 600) {
compiler->reg_size_vec4 =
fd_dev_info(compiler->gpu_id)->a6xx.reg_size_vec4;
} else if (compiler->gpu_id >= 400) {
/* On a4xx-a5xx, using r24.x and above requires using the smallest
* threadsize.