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intel: fix typos found by codespell

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Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
This commit is contained in:
Marcin Ślusarz
2022-06-22 18:31:08 +02:00
committed by Marge Bot
parent ab0e09803a
commit f4386b81e6
64 changed files with 141 additions and 141 deletions
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4
src/intel/vulkan/genX_blorp_exec.c
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@@ -288,7 +288,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
#if GFX_VER >= 11
/* The PIPE_CONTROL command description says:
*
* "Whenever a Binding Table Index (BTI) used by a Render Taget Message
* "Whenever a Binding Table Index (BTI) used by a Render Target Message
* points to a different RENDER_SURFACE_STATE, SW must issue a Render
* Target Cache Flush by enabling this bit. When render target flush
* is set due to new association of BTI, PS Scoreboard Stall bit must
@@ -321,7 +321,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
#if GFX_VER >= 11
/* The PIPE_CONTROL command description says:
*
* "Whenever a Binding Table Index (BTI) used by a Render Taget Message
* "Whenever a Binding Table Index (BTI) used by a Render Target Message
* points to a different RENDER_SURFACE_STATE, SW must issue a Render
* Target Cache Flush by enabling this bit. When render target flush
* is set due to new association of BTI, PS Scoreboard Stall bit must