nv50/ir: change texture offsets to ValueRefs, allow nonconst
This allows us to have non-constant offsets for textureGatherOffset and textureGatherOffsets. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
@@ -911,6 +911,9 @@ TexInstruction::~TexInstruction()
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dPdx[c].set(NULL);
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dPdy[c].set(NULL);
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}
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for (int n = 0; n < 4; ++n)
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for (int c = 0; c < 3; ++c)
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offset[n][c].set(NULL);
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}
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TexInstruction *
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@@ -930,6 +933,10 @@ TexInstruction::clone(ClonePolicy<Function>& pol, Instruction *i) const
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}
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}
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for (int n = 0; n < tex->tex.useOffsets; ++n)
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for (int c = 0; c < 3; ++c)
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tex->offset[n][c].set(offset[n][c]);
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return tex;
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}
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@@ -913,13 +913,14 @@ public:
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bool derivAll;
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int8_t useOffsets; // 0, 1, or 4 for textureGatherOffsets
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int8_t offset[4][3];
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int8_t offset[3]; // only used on nv50
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enum TexQuery query;
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} tex;
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ValueRef dPdx[3];
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ValueRef dPdy[3];
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ValueRef offset[4][3];
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};
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class CmpInstruction : public Instruction
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@@ -1104,12 +1104,14 @@ CodeEmitterGK110::emitTEX(const TexInstruction *i)
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// ?
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}
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if (i->tex.useOffsets) {
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if (i->tex.useOffsets == 1) {
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switch (i->op) {
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case OP_TXF: code[1] |= 0x200; break;
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default: code[1] |= 0x800; break;
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}
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}
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if (i->tex.useOffsets == 4)
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code[1] |= 0x1000;
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}
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void
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@@ -1475,9 +1475,9 @@ CodeEmitterNV50::emitTEX(const TexInstruction *i)
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code[0] |= 0x08000000;
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} else
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if (i->tex.useOffsets) {
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code[1] |= (i->tex.offset[0][0] & 0xf) << 24;
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code[1] |= (i->tex.offset[0][1] & 0xf) << 20;
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code[1] |= (i->tex.offset[0][2] & 0xf) << 16;
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code[1] |= (i->tex.offset[0] & 0xf) << 24;
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code[1] |= (i->tex.offset[1] & 0xf) << 20;
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code[1] |= (i->tex.offset[2] & 0xf) << 16;
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}
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code[0] |= (i->tex.mask & 0x3) << 25;
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@@ -1208,8 +1208,10 @@ CodeEmitterNVC0::emitTEX(const TexInstruction *i)
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i->tex.target == TEX_TARGET_2D_MS_ARRAY)
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code[1] |= 1 << 23;
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if (i->tex.useOffsets) // in vecSrc0.w
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if (i->tex.useOffsets == 1)
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code[1] |= 1 << 22;
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if (i->tex.useOffsets == 4)
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code[1] |= 1 << 23;
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srcId(i, src1, 26);
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}
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@@ -1763,11 +1763,11 @@ Converter::handleTEX(Value *dst[4], int R, int S, int L, int C, int Dx, int Dy)
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if (tgsi.getOpcode() == TGSI_OPCODE_TG4 && !tgt.isShadow())
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texi->tex.gatherComp = tgsi.getSrc(1).getValueU32(0, info);
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texi->tex.useOffsets = tgsi.getNumTexOffsets();
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for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
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for (c = 0; c < 3; ++c) {
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texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
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if (texi->tex.offset[s][c])
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texi->tex.useOffsets = s + 1;
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texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
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texi->offset[s][c].setInsn(texi);
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}
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}
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@@ -1800,11 +1800,11 @@ Converter::handleTXF(Value *dst[4], int R, int L_M)
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setTexRS(texi, c, R, -1);
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texi->tex.useOffsets = tgsi.getNumTexOffsets();
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for (s = 0; s < tgsi.getNumTexOffsets(); ++s) {
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for (c = 0; c < 3; ++c) {
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texi->tex.offset[s][c] = tgsi.getTexOffset(s).getValueU32(c, info);
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if (texi->tex.offset[s][c])
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texi->tex.useOffsets = s + 1;
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texi->offset[s][c].set(fetchSrc(tgsi.getTexOffset(s), c, NULL));
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texi->offset[s][c].setInsn(texi);
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}
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}
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@@ -695,6 +695,14 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
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// texel offsets are 3 immediate fields in the instruction,
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// nv50 cannot do textureGatherOffsets
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assert(i->tex.useOffsets <= 1);
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if (i->tex.useOffsets) {
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for (int c = 0; c < 3; ++c) {
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ImmediateValue val;
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assert(i->offset[0][c].getImmediate(val));
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i->tex.offset[c] = val.reg.data.u32;
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i->offset[0][c].set(NULL);
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}
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}
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return true;
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}
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@@ -739,21 +739,42 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
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// offset is last source (lod 1st, dc 2nd)
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if (i->tex.useOffsets) {
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uint32_t value = 0;
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int n, c;
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int s = i->srcCount(0xff, true);
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if (i->srcExists(s)) // move potential predicate out of the way
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i->moveSources(s, 1);
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if (i->tex.useOffsets == 4 && i->srcExists(s + 1))
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i->moveSources(s + 1, 1);
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if (i->op == OP_TXG) {
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assert(i->tex.useOffsets == 1);
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for (c = 0; c < 3; ++c)
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value |= (i->tex.offset[0][c] & 0xff) << (c * 8);
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// Either there is 1 offset, which goes into the 2 low bytes of the
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// first source, or there are 4 offsets, which go into 2 sources (8
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// values, 1 byte each).
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Value *offs[2] = {NULL, NULL};
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for (n = 0; n < i->tex.useOffsets; n++) {
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for (c = 0; c < 2; ++c) {
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if ((n % 2) == 0 && c == 0)
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offs[n / 2] = i->offset[n][c].get();
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else
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bld.mkOp3(OP_INSBF, TYPE_U32,
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offs[n / 2],
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i->offset[n][c].get(),
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bld.mkImm(0x800 | ((n * 16 + c * 8) % 32)),
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offs[n / 2]);
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}
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}
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i->setSrc(s, offs[0]);
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if (offs[1])
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i->setSrc(s + 1, offs[1]);
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} else {
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for (n = 0; n < i->tex.useOffsets; ++n)
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for (c = 0; c < 3; ++c)
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value |= (i->tex.offset[n][c] & 0xf) << (n * 12 + c * 4);
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unsigned imm = 0;
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assert(i->tex.useOffsets == 1);
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for (c = 0; c < 3; ++c) {
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ImmediateValue val;
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assert(i->offset[0][c].getImmediate(val));
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imm |= (val.reg.data.u32 & 0xf) << (c * 4);
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}
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i->setSrc(s, bld.loadImm(NULL, imm));
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}
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i->setSrc(s, bld.loadImm(NULL, value));
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}
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if (chipset >= NVISA_GK104_CHIPSET) {
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