radv: add support for shader stats dump
I've started working on a shader-db alike for Vulkan, it's based on vktrace and it records pipelines, this adds support to dump the shader stats exactly like radeonsi does, so I can reuse the shader-db scripts it uses. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
@@ -666,6 +666,7 @@ VkResult radv_CreateDevice(
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}
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}
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device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
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device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
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device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
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device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
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device->shader_stats_dump = env_var_as_boolean("RADV_SHADER_STATS", false);
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if (device->allow_fast_clears && device->allow_dcc)
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if (device->allow_fast_clears && device->allow_dcc)
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radv_finishme("DCC fast clears have not been tested\n");
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radv_finishme("DCC fast clears have not been tested\n");
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@@ -257,6 +257,81 @@ radv_shader_compile_to_nir(struct radv_device *device,
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return nir;
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return nir;
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}
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}
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static const char *radv_get_shader_name(struct radv_shader_variant *var,
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gl_shader_stage stage)
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{
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switch (stage) {
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case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
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case MESA_SHADER_FRAGMENT: return "Pixel Shader";
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case MESA_SHADER_COMPUTE: return "Compute Shader";
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default:
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return "Unknown shader";
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};
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}
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static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
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{
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unsigned lds_increment = device->instance->physicalDevice.rad_info.chip_class >= CIK ? 512 : 256;
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struct radv_shader_variant *var;
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struct ac_shader_config *conf;
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int i;
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FILE *file = stderr;
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unsigned max_simd_waves = 10;
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unsigned lds_per_wave = 0;
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for (i = 0; i < MESA_SHADER_STAGES; i++) {
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if (!pipeline->shaders[i])
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continue;
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var = pipeline->shaders[i];
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conf = &var->config;
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if (i == MESA_SHADER_FRAGMENT) {
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lds_per_wave = conf->lds_size * lds_increment +
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align(var->info.fs.num_interp * 48, lds_increment);
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}
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if (conf->num_sgprs) {
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if (device->instance->physicalDevice.rad_info.chip_class >= VI)
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max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
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else
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max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
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}
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if (conf->num_vgprs)
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max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
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/* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
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* that PS can use.
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*/
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if (lds_per_wave)
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max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
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fprintf(file, "\n%s:\n",
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radv_get_shader_name(var, i));
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if (i == MESA_SHADER_FRAGMENT) {
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fprintf(file, "*** SHADER CONFIG ***\n"
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"SPI_PS_INPUT_ADDR = 0x%04x\n"
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"SPI_PS_INPUT_ENA = 0x%04x\n",
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conf->spi_ps_input_addr, conf->spi_ps_input_ena);
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}
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fprintf(file, "*** SHADER STATS ***\n"
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"SGPRS: %d\n"
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"VGPRS: %d\n"
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"Spilled SGPRs: %d\n"
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"Spilled VGPRs: %d\n"
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"Code Size: %d bytes\n"
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"LDS: %d blocks\n"
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"Scratch: %d bytes per wave\n"
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"Max Waves: %d\n"
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"********************\n\n\n",
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conf->num_sgprs, conf->num_vgprs,
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conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
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conf->lds_size, conf->scratch_bytes_per_wave,
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max_simd_waves);
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}
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}
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void radv_shader_variant_destroy(struct radv_device *device,
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void radv_shader_variant_destroy(struct radv_device *device,
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struct radv_shader_variant *variant)
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struct radv_shader_variant *variant)
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{
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{
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@@ -297,6 +372,7 @@ struct radv_shader_variant *radv_shader_variant_create(struct radv_device *devic
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&variant->info, shader, &options, dump);
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&variant->info, shader, &options, dump);
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LLVMDisposeTargetMachine(tm);
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LLVMDisposeTargetMachine(tm);
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variant->code_size = binary.code_size;
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bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
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bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
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unsigned vgpr_comp_cnt = 0;
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unsigned vgpr_comp_cnt = 0;
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@@ -1319,6 +1395,10 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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pipeline->binding_stride[desc->binding] = desc->stride;
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pipeline->binding_stride[desc->binding] = desc->stride;
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}
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}
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if (device->shader_stats_dump) {
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radv_dump_pipeline_stats(device, pipeline);
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}
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return VK_SUCCESS;
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return VK_SUCCESS;
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}
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}
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@@ -1412,6 +1492,10 @@ static VkResult radv_compute_pipeline_create(
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pipeline->layout, NULL, dump);
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pipeline->layout, NULL, dump);
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*pPipeline = radv_pipeline_to_handle(pipeline);
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*pPipeline = radv_pipeline_to_handle(pipeline);
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if (device->shader_stats_dump) {
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radv_dump_pipeline_stats(device, pipeline);
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}
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return VK_SUCCESS;
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return VK_SUCCESS;
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}
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}
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VkResult radv_CreateComputePipelines(
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VkResult radv_CreateComputePipelines(
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@@ -444,6 +444,7 @@ struct radv_device {
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bool allow_fast_clears;
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bool allow_fast_clears;
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bool allow_dcc;
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bool allow_dcc;
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bool shader_stats_dump;
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/* MSAA sample locations.
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/* MSAA sample locations.
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* The first index is the sample index.
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* The first index is the sample index.
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@@ -794,6 +795,7 @@ struct radv_shader_variant {
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struct ac_shader_variant_info info;
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struct ac_shader_variant_info info;
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unsigned rsrc1;
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unsigned rsrc1;
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unsigned rsrc2;
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unsigned rsrc2;
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uint32_t code_size;
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};
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};
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struct radv_depth_stencil_state {
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struct radv_depth_stencil_state {
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