nir/lower_io: Add "explicit" IO lowering
This new pass is for lowering explicitly laid out memory coming in from SPIR-V or a similar source. It's quite a bit more complicated than the normal lower_io because we have to be able to handle matrices. The way the stride information is stored for matrices is awkward and dealing with row-major matrices is especially painful. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
committed by
Jason Ekstrand
Jason Ekstrand
parent
52dd43c7ef
commit
f393b10b3f
@@ -2896,6 +2896,18 @@ bool nir_lower_io(nir_shader *shader,
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nir_variable_mode modes,
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nir_variable_mode modes,
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int (*type_size)(const struct glsl_type *),
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int (*type_size)(const struct glsl_type *),
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nir_lower_io_options);
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nir_lower_io_options);
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typedef enum {
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/**
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* An address format which is comprised of a vec2 where the first
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* component is a vulkan descriptor index and the second is an offset.
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*/
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nir_address_format_vk_index_offset,
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} nir_address_format;
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bool nir_lower_explicit_io(nir_shader *shader,
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nir_variable_mode modes,
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nir_address_format);
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nir_src *nir_get_io_offset_src(nir_intrinsic_instr *instr);
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nir_src *nir_get_io_offset_src(nir_intrinsic_instr *instr);
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nir_src *nir_get_io_vertex_index_src(nir_intrinsic_instr *instr);
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nir_src *nir_get_io_vertex_index_src(nir_intrinsic_instr *instr);
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@@ -528,6 +528,411 @@ nir_lower_io(nir_shader *shader, nir_variable_mode modes,
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return progress;
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return progress;
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}
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}
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static unsigned
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type_scalar_size_bytes(const struct glsl_type *type)
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{
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assert(glsl_type_is_vector_or_scalar(type) ||
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glsl_type_is_matrix(type));
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return glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
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}
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static nir_ssa_def *
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build_addr_iadd(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format, nir_ssa_def *offset)
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{
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assert(offset->num_components == 1);
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assert(addr->bit_size == offset->bit_size);
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switch (addr_format) {
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case nir_address_format_vk_index_offset:
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assert(addr->num_components == 2);
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return nir_vec2(b, nir_channel(b, addr, 0),
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nir_iadd(b, nir_channel(b, addr, 1), offset));
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}
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unreachable("Invalid address format");
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}
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static nir_ssa_def *
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build_addr_iadd_imm(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format, int64_t offset)
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{
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return build_addr_iadd(b, addr, addr_format,
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nir_imm_intN_t(b, offset, addr->bit_size));
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}
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static nir_ssa_def *
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addr_to_index(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format)
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{
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assert(addr_format == nir_address_format_vk_index_offset);
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assert(addr->num_components == 2);
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return nir_channel(b, addr, 0);
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}
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static nir_ssa_def *
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addr_to_offset(nir_builder *b, nir_ssa_def *addr,
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nir_address_format addr_format)
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{
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assert(addr_format == nir_address_format_vk_index_offset);
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assert(addr->num_components == 2);
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return nir_channel(b, addr, 1);
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}
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static nir_ssa_def *
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build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin,
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nir_ssa_def *addr, nir_address_format addr_format,
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unsigned num_components)
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{
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nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
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nir_intrinsic_op op;
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switch (mode) {
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case nir_var_ubo:
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op = nir_intrinsic_load_ubo;
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break;
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case nir_var_ssbo:
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op = nir_intrinsic_load_ssbo;
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break;
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default:
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unreachable("Unsupported explicit IO variable mode");
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}
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nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, op);
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load->src[0] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
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load->src[1] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
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if (mode != nir_var_ubo)
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nir_intrinsic_set_access(load, nir_intrinsic_access(intrin));
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/* TODO: We should try and provide a better alignment. For OpenCL, we need
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* to plumb the alignment through from SPIR-V when we have one.
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*/
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nir_intrinsic_set_align(load, intrin->dest.ssa.bit_size / 8, 0);
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assert(intrin->dest.is_ssa);
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load->num_components = num_components;
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nir_ssa_dest_init(&load->instr, &load->dest, num_components,
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intrin->dest.ssa.bit_size, intrin->dest.ssa.name);
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nir_builder_instr_insert(b, &load->instr);
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return &load->dest.ssa;
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}
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static void
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build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin,
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nir_ssa_def *addr, nir_address_format addr_format,
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nir_ssa_def *value, nir_component_mask_t write_mask)
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{
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nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
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nir_intrinsic_op op;
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switch (mode) {
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case nir_var_ssbo:
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op = nir_intrinsic_store_ssbo;
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break;
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default:
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unreachable("Unsupported explicit IO variable mode");
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}
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, op);
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store->src[0] = nir_src_for_ssa(value);
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store->src[1] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
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store->src[2] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
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nir_intrinsic_set_write_mask(store, write_mask);
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nir_intrinsic_set_access(store, nir_intrinsic_access(intrin));
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/* TODO: We should try and provide a better alignment. For OpenCL, we need
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* to plumb the alignment through from SPIR-V when we have one.
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*/
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nir_intrinsic_set_align(store, value->bit_size / 8, 0);
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assert(value->num_components == 1 ||
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value->num_components == intrin->num_components);
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store->num_components = value->num_components;
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nir_builder_instr_insert(b, &store->instr);
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}
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static nir_ssa_def *
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build_explicit_io_atomic(nir_builder *b, nir_intrinsic_instr *intrin,
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nir_ssa_def *addr, nir_address_format addr_format)
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{
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nir_variable_mode mode = nir_src_as_deref(intrin->src[0])->mode;
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const unsigned num_data_srcs =
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nir_intrinsic_infos[intrin->intrinsic].num_srcs - 1;
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nir_intrinsic_op op;
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switch (mode) {
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case nir_var_ssbo:
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switch (intrin->intrinsic) {
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#define OP(O) case nir_intrinsic_deref_##O: op = nir_intrinsic_ssbo_##O; break;
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OP(atomic_exchange)
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OP(atomic_comp_swap)
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OP(atomic_add)
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OP(atomic_imin)
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OP(atomic_umin)
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OP(atomic_imax)
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OP(atomic_umax)
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OP(atomic_and)
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OP(atomic_or)
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OP(atomic_xor)
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OP(atomic_fadd)
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OP(atomic_fmin)
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OP(atomic_fmax)
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OP(atomic_fcomp_swap)
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#undef OP
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default:
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unreachable("Invalid SSBO atomic");
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}
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break;
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default:
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unreachable("Unsupported explicit IO variable mode");
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}
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nir_intrinsic_instr *atomic = nir_intrinsic_instr_create(b->shader, op);
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atomic->src[0] = nir_src_for_ssa(addr_to_index(b, addr, addr_format));
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atomic->src[1] = nir_src_for_ssa(addr_to_offset(b, addr, addr_format));
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for (unsigned i = 0; i < num_data_srcs; i++) {
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assert(intrin->src[1 + i].is_ssa);
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atomic->src[2 + i] = nir_src_for_ssa(intrin->src[1 + i].ssa);
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}
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assert(intrin->dest.ssa.num_components == 1);
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nir_ssa_dest_init(&atomic->instr, &atomic->dest,
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1, intrin->dest.ssa.bit_size, intrin->dest.ssa.name);
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nir_builder_instr_insert(b, &atomic->instr);
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return &atomic->dest.ssa;
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}
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static void
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lower_explicit_io_deref(nir_builder *b, nir_deref_instr *deref,
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nir_address_format addr_format)
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{
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/* Just delete the deref if it's not used. We can't use
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* nir_deref_instr_remove_if_unused here because it may remove more than
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* one deref which could break our list walking since we walk the list
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* backwards.
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*/
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assert(list_empty(&deref->dest.ssa.if_uses));
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if (list_empty(&deref->dest.ssa.uses)) {
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nir_instr_remove(&deref->instr);
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return;
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}
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b->cursor = nir_after_instr(&deref->instr);
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/* Var derefs must be lowered away by the driver */
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assert(deref->deref_type != nir_deref_type_var);
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assert(deref->parent.is_ssa);
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nir_ssa_def *parent_addr = deref->parent.ssa;
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nir_ssa_def *addr;
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assert(deref->dest.is_ssa);
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switch (deref->deref_type) {
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case nir_deref_type_var:
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unreachable("Must be lowered by the driver");
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break;
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case nir_deref_type_array: {
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nir_deref_instr *parent = nir_deref_instr_parent(deref);
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unsigned stride = glsl_get_explicit_stride(parent->type);
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if ((glsl_type_is_matrix(parent->type) &&
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glsl_matrix_type_is_row_major(parent->type)) ||
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(glsl_type_is_vector(parent->type) && stride == 0))
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stride = type_scalar_size_bytes(parent->type);
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assert(stride > 0);
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nir_ssa_def *index = nir_ssa_for_src(b, deref->arr.index, 1);
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index = nir_i2i(b, index, parent_addr->bit_size);
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addr = build_addr_iadd(b, parent_addr, addr_format,
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nir_imul_imm(b, index, stride));
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break;
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}
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case nir_deref_type_ptr_as_array: {
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nir_ssa_def *index = nir_ssa_for_src(b, deref->arr.index, 1);
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index = nir_i2i(b, index, parent_addr->bit_size);
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unsigned stride = nir_deref_instr_ptr_as_array_stride(deref);
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addr = build_addr_iadd(b, parent_addr, addr_format,
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nir_imul_imm(b, index, stride));
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break;
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}
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case nir_deref_type_array_wildcard:
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unreachable("Wildcards should be lowered by now");
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break;
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case nir_deref_type_struct: {
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nir_deref_instr *parent = nir_deref_instr_parent(deref);
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int offset = glsl_get_struct_field_offset(parent->type,
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deref->strct.index);
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assert(offset >= 0);
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addr = build_addr_iadd_imm(b, parent_addr, addr_format, offset);
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break;
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}
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case nir_deref_type_cast:
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/* Nothing to do here */
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addr = parent_addr;
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break;
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}
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nir_instr_remove(&deref->instr);
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nir_ssa_def_rewrite_uses(&deref->dest.ssa, nir_src_for_ssa(addr));
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}
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static void
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lower_explicit_io_access(nir_builder *b, nir_intrinsic_instr *intrin,
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nir_address_format addr_format)
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{
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b->cursor = nir_after_instr(&intrin->instr);
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nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
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unsigned vec_stride = glsl_get_explicit_stride(deref->type);
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unsigned scalar_size = type_scalar_size_bytes(deref->type);
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assert(vec_stride == 0 || glsl_type_is_vector(deref->type));
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assert(vec_stride == 0 || vec_stride >= scalar_size);
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nir_ssa_def *addr = &deref->dest.ssa;
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if (intrin->intrinsic == nir_intrinsic_load_deref) {
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nir_ssa_def *value;
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if (vec_stride > scalar_size) {
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nir_ssa_def *comps[4] = { NULL, };
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for (unsigned i = 0; i < intrin->num_components; i++) {
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nir_ssa_def *comp_addr = build_addr_iadd_imm(b, addr, addr_format,
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vec_stride * i);
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comps[i] = build_explicit_io_load(b, intrin, comp_addr,
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addr_format, 1);
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}
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value = nir_vec(b, comps, intrin->num_components);
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} else {
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value = build_explicit_io_load(b, intrin, addr, addr_format,
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intrin->num_components);
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}
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(value));
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} else if (intrin->intrinsic == nir_intrinsic_store_deref) {
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assert(intrin->src[1].is_ssa);
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nir_ssa_def *value = intrin->src[1].ssa;
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nir_component_mask_t write_mask = nir_intrinsic_write_mask(intrin);
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if (vec_stride > scalar_size) {
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for (unsigned i = 0; i < intrin->num_components; i++) {
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if (!(write_mask & (1 << i)))
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continue;
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nir_ssa_def *comp_addr = build_addr_iadd_imm(b, addr, addr_format,
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vec_stride * i);
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build_explicit_io_store(b, intrin, comp_addr, addr_format,
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nir_channel(b, value, i), 1);
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}
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} else {
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build_explicit_io_store(b, intrin, addr, addr_format,
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value, write_mask);
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}
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} else {
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nir_ssa_def *value =
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build_explicit_io_atomic(b, intrin, addr, addr_format);
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||||||
|
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(value));
|
||||||
|
}
|
||||||
|
|
||||||
|
nir_instr_remove(&intrin->instr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool
|
||||||
|
nir_lower_explicit_io_impl(nir_function_impl *impl, nir_variable_mode modes,
|
||||||
|
nir_address_format addr_format)
|
||||||
|
{
|
||||||
|
bool progress = false;
|
||||||
|
|
||||||
|
nir_builder b;
|
||||||
|
nir_builder_init(&b, impl);
|
||||||
|
|
||||||
|
/* Walk in reverse order so that we can see the full deref chain when we
|
||||||
|
* lower the access operations. We lower them assuming that the derefs
|
||||||
|
* will be turned into address calculations later.
|
||||||
|
*/
|
||||||
|
nir_foreach_block_reverse(block, impl) {
|
||||||
|
nir_foreach_instr_reverse_safe(instr, block) {
|
||||||
|
switch (instr->type) {
|
||||||
|
case nir_instr_type_deref: {
|
||||||
|
nir_deref_instr *deref = nir_instr_as_deref(instr);
|
||||||
|
if (deref->mode & modes) {
|
||||||
|
lower_explicit_io_deref(&b, deref, addr_format);
|
||||||
|
progress = true;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
case nir_instr_type_intrinsic: {
|
||||||
|
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
||||||
|
switch (intrin->intrinsic) {
|
||||||
|
case nir_intrinsic_load_deref:
|
||||||
|
case nir_intrinsic_store_deref:
|
||||||
|
case nir_intrinsic_deref_atomic_add:
|
||||||
|
case nir_intrinsic_deref_atomic_imin:
|
||||||
|
case nir_intrinsic_deref_atomic_umin:
|
||||||
|
case nir_intrinsic_deref_atomic_imax:
|
||||||
|
case nir_intrinsic_deref_atomic_umax:
|
||||||
|
case nir_intrinsic_deref_atomic_and:
|
||||||
|
case nir_intrinsic_deref_atomic_or:
|
||||||
|
case nir_intrinsic_deref_atomic_xor:
|
||||||
|
case nir_intrinsic_deref_atomic_exchange:
|
||||||
|
case nir_intrinsic_deref_atomic_comp_swap:
|
||||||
|
case nir_intrinsic_deref_atomic_fadd:
|
||||||
|
case nir_intrinsic_deref_atomic_fmin:
|
||||||
|
case nir_intrinsic_deref_atomic_fmax:
|
||||||
|
case nir_intrinsic_deref_atomic_fcomp_swap: {
|
||||||
|
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
|
||||||
|
if (deref->mode & modes) {
|
||||||
|
lower_explicit_io_access(&b, intrin, addr_format);
|
||||||
|
progress = true;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
default:
|
||||||
|
/* Nothing to do */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (progress) {
|
||||||
|
nir_metadata_preserve(impl, nir_metadata_block_index |
|
||||||
|
nir_metadata_dominance);
|
||||||
|
}
|
||||||
|
|
||||||
|
return progress;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool
|
||||||
|
nir_lower_explicit_io(nir_shader *shader, nir_variable_mode modes,
|
||||||
|
nir_address_format addr_format)
|
||||||
|
{
|
||||||
|
bool progress = false;
|
||||||
|
|
||||||
|
nir_foreach_function(function, shader) {
|
||||||
|
if (function->impl &&
|
||||||
|
nir_lower_explicit_io_impl(function->impl, modes, addr_format))
|
||||||
|
progress = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
return progress;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return the offset source for a load/store intrinsic.
|
* Return the offset source for a load/store intrinsic.
|
||||||
*/
|
*/
|
||||||
|
|||||||
Reference in New Issue
Block a user