From f34975cdf9ad68f75df49d854208dfb258fbded9 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 30 Aug 2022 15:57:19 -0700 Subject: [PATCH] anv: Delete shader constants UBO from descriptor sets We now always softpin and use the load_global_constant case, so there's no need to set up a UBO for NIR constants. Reviewed-by: Lionel Landwerlin Part-of: --- .../vulkan/anv_nir_apply_pipeline_layout.c | 48 ++++++------------- src/intel/vulkan/anv_pipeline.c | 5 -- src/intel/vulkan/anv_private.h | 9 ++-- src/intel/vulkan/genX_cmd_buffer.c | 35 -------------- 4 files changed, 19 insertions(+), 78 deletions(-) diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index c58c851ae46..0821336c8d7 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -1057,35 +1057,24 @@ lower_load_constant(nir_builder *b, nir_intrinsic_instr *intrin, nir_ssa_def *offset = nir_iadd_imm(b, nir_ssa_for_src(b, intrin->src[0], 1), nir_intrinsic_base(intrin)); - nir_ssa_def *data; - if (!anv_use_relocations(state->pdevice)) { - unsigned load_size = intrin->dest.ssa.num_components * - intrin->dest.ssa.bit_size / 8; - unsigned load_align = intrin->dest.ssa.bit_size / 8; + unsigned load_size = intrin->dest.ssa.num_components * + intrin->dest.ssa.bit_size / 8; + unsigned load_align = intrin->dest.ssa.bit_size / 8; - assert(load_size < b->shader->constant_data_size); - unsigned max_offset = b->shader->constant_data_size - load_size; - offset = nir_umin(b, offset, nir_imm_int(b, max_offset)); + assert(load_size < b->shader->constant_data_size); + unsigned max_offset = b->shader->constant_data_size - load_size; + offset = nir_umin(b, offset, nir_imm_int(b, max_offset)); - nir_ssa_def *const_data_base_addr = nir_pack_64_2x32_split(b, - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW), - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH)); + nir_ssa_def *const_data_base_addr = nir_pack_64_2x32_split(b, + nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW), + nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH)); - data = nir_load_global_constant(b, nir_iadd(b, const_data_base_addr, - nir_u2u64(b, offset)), - load_align, - intrin->dest.ssa.num_components, - intrin->dest.ssa.bit_size); - } else { - nir_ssa_def *index = nir_imm_int(b, state->constants_offset); - - data = nir_load_ubo(b, intrin->num_components, intrin->dest.ssa.bit_size, - index, offset, - .align_mul = intrin->dest.ssa.bit_size / 8, - .align_offset = 0, - .range_base = nir_intrinsic_base(intrin), - .range = nir_intrinsic_range(intrin)); - } + nir_ssa_def *data = + nir_load_global_constant(b, nir_iadd(b, const_data_base_addr, + nir_u2u64(b, offset)), + load_align, + intrin->dest.ssa.num_components, + intrin->dest.ssa.bit_size); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, data); @@ -1369,13 +1358,6 @@ anv_nir_apply_pipeline_layout(nir_shader *shader, } } - if (state.uses_constants && anv_use_relocations(pdevice)) { - state.constants_offset = map->surface_count; - map->surface_to_descriptor[map->surface_count].set = - ANV_DESCRIPTOR_SET_SHADER_CONSTANTS; - map->surface_count++; - } - unsigned used_binding_count = 0; for (uint32_t set = 0; set < layout->num_sets; set++) { struct anv_descriptor_set_layout *set_layout = layout->set[set].layout; diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 1567e23a293..feba1b50bf2 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1216,11 +1216,6 @@ anv_pipeline_add_executable(struct anv_pipeline *pipeline, case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: unreachable("gl_NumWorkgroups is never pushed"); - case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: - fprintf(stream, "Inline shader constant data (start=%dB)", - stage->bind_map.push_ranges[i].start * 32); - break; - case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS: unreachable("Color attachments can't be pushed"); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 500c94793ba..aaa556f2165 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2097,11 +2097,10 @@ anv_descriptor_set_write_template(struct anv_device *device, const struct anv_descriptor_update_template *template, const void *data); -#define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 5) -#define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 4) -#define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 3) -#define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 2) -#define ANV_DESCRIPTOR_SET_SHADER_CONSTANTS (UINT8_MAX - 1) +#define ANV_DESCRIPTOR_SET_NULL (UINT8_MAX - 4) +#define ANV_DESCRIPTOR_SET_PUSH_CONSTANTS (UINT8_MAX - 3) +#define ANV_DESCRIPTOR_SET_DESCRIPTORS (UINT8_MAX - 2) +#define ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS (UINT8_MAX - 1) #define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX struct anv_pipeline_binding { diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5777877853b..f9e991d5962 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2355,31 +2355,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, bt_map[s] = surface_state.offset + state_offset; break; - case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: { - struct anv_state surface_state = - anv_cmd_buffer_alloc_surface_state(cmd_buffer); - - struct anv_address constant_data = { - .bo = cmd_buffer->device->instruction_state_pool.block_pool.bo, - .offset = shader->kernel.offset + - shader->prog_data->const_data_offset, - }; - unsigned constant_data_size = shader->prog_data->const_data_size; - - const enum isl_format format = - anv_isl_format_for_descriptor_type(cmd_buffer->device, - VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER); - anv_fill_buffer_surface_state(cmd_buffer->device, surface_state, - format, ISL_SWIZZLE_IDENTITY, - ISL_SURF_USAGE_CONSTANT_BUFFER_BIT, - constant_data, constant_data_size, 1); - - assert(surface_state.map); - bt_map[s] = surface_state.offset + state_offset; - add_surface_reloc(cmd_buffer, surface_state, constant_data); - break; - } - case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS: { /* This is always the first binding for compute shaders */ assert(shader->stage == MESA_SHADER_COMPUTE && s == 0); @@ -2778,13 +2753,6 @@ get_push_range_address(struct anv_cmd_buffer *cmd_buffer, }; } - case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: - return (struct anv_address) { - .bo = cmd_buffer->device->instruction_state_pool.block_pool.bo, - .offset = shader->kernel.offset + - shader->prog_data->const_data_offset, - }; - default: { assert(range->set < MAX_SETS); struct anv_descriptor_set *set = @@ -2847,9 +2815,6 @@ get_push_range_bound_size(struct anv_cmd_buffer *cmd_buffer, case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS: return (range->start + range->length) * 32; - case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS: - return ALIGN(shader->prog_data->const_data_size, ANV_UBO_ALIGNMENT); - default: { assert(range->set < MAX_SETS); struct anv_descriptor_set *set =