OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

winsys/radeon: revert recent changes

Browse Source 
This reverts commit f673e2bf68.
This reverts commit 216ff9591b.
This reverts commit ec2451fcb3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30228>
This commit is contained in:
Mike Blumenkrantz
2024-07-17 12:18:00 -04:00
committed by Marge Bot
parent cc9503206e
commit f24742e8dc
3 changed files with 46 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
View File

@@ -1090,7 +1090,7 @@ static struct pb_buffer_lean *radeon_winsys_bo_from_ptr(struct radeon_winsys *rw
RADEON_GEM_USERPTR_REGISTER |
RADEON_GEM_USERPTR_VALIDATE;
if (drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_GEM_USERPTR,
if (drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
&args, sizeof(args))) {
FREE(bo);
return NULL;
@@ -1129,7 +1129,7 @@ static struct pb_buffer_lean *radeon_winsys_bo_from_ptr(struct radeon_winsys *rw
RADEON_VM_PAGE_WRITEABLE |
RADEON_VM_PAGE_SNOOPED;
va.offset = bo->va;
r = drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_GEM_VA, &va, sizeof(va));
r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
if (r && va.operation == RADEON_VA_RESULT_ERROR) {
fprintf(stderr, "radeon: Failed to assign virtual address space\n");
radeon_bo_destroy(NULL, &bo->base);
@@ -1179,16 +1179,7 @@ static struct pb_buffer_lean *radeon_winsys_bo_from_handle(struct radeon_winsys
bo = util_hash_table_get(ws->bo_names, (void*)(uintptr_t)whandle->handle);
} else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
/* We must first get the GEM handle, as fds are unreliable keys */
if (ws->rendernode_fd != -1) {
int handle2;
r = drmPrimeHandleToFD(ws->rendernode_fd, whandle->handle, DRM_CLOEXEC, &handle2);
if (r)
goto fail;
r = drmPrimeFDToHandle(ws->fd, handle2, &handle);
close(handle2);
} else {
r = drmPrimeFDToHandle(ws->fd, whandle->handle, &handle);
}
r = drmPrimeFDToHandle(ws->fd, whandle->handle, &handle);
if (r)
goto fail;
bo = util_hash_table_get(ws->bo_handles, (void*)(uintptr_t)handle);
@@ -1214,7 +1205,7 @@ static struct pb_buffer_lean *radeon_winsys_bo_from_handle(struct radeon_winsys
memset(&open_arg, 0, sizeof(open_arg));
/* Open the BO. */
open_arg.name = whandle->handle;
if (drmIoctl(radeon_drm_winsys_fd(ws), DRM_IOCTL_GEM_OPEN, &open_arg)) {
if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
FREE(bo);
goto fail;
}
@@ -1268,7 +1259,7 @@ done:
RADEON_VM_PAGE_WRITEABLE |
RADEON_VM_PAGE_SNOOPED;
va.offset = bo->va;
r = drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_GEM_VA, &va, sizeof(va));
r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
if (r && va.operation == RADEON_VA_RESULT_ERROR) {
fprintf(stderr, "radeon: Failed to assign virtual address space\n");
radeon_bo_destroy(NULL, &bo->base);
@@ -1323,7 +1314,7 @@ static bool radeon_winsys_bo_get_handle(struct radeon_winsys *rws,
if (!bo->flink_name) {
flink.handle = bo->handle;
if (ioctl(radeon_drm_winsys_fd(ws), DRM_IOCTL_GEM_FLINK, &flink)) {
if (ioctl(ws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
return false;
}
@@ -1337,7 +1328,7 @@ static bool radeon_winsys_bo_get_handle(struct radeon_winsys *rws,
} else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
whandle->handle = bo->handle;
} else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
if (drmPrimeHandleToFD(radeon_drm_winsys_fd(ws), bo->handle, DRM_CLOEXEC, (int*)&whandle->handle))
if (drmPrimeHandleToFD(ws->fd, bo->handle, DRM_CLOEXEC, (int*)&whandle->handle))
return false;
}

91
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View File

@@ -62,7 +62,7 @@ static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
/* Pass through the request to the kernel. */
info.value = (unsigned long)&value;
info.request = request;
if (drmCommandWriteRead(radeon_drm_winsys_fd(applier->ws), DRM_RADEON_INFO,
if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
&info, sizeof(info)) != 0) {
mtx_unlock(&*mutex);
return false;
@@ -83,7 +83,7 @@ static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
return false;
}
static bool radeon_get_drm_value(struct radeon_drm_winsys *ws, unsigned request,
static bool radeon_get_drm_value(int fd, unsigned request,
const char *errname, uint32_t *out)
{
struct drm_radeon_info info;
@@ -94,16 +94,8 @@ static bool radeon_get_drm_value(struct radeon_drm_winsys *ws, unsigned request,
info.value = (unsigned long)out;
info.request = request;
retval = drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_INFO, &info, sizeof(info));
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
if (retval) {
/* try switching over to a render node */
if (retval == -EACCES && ws->rendernode_fd == -1) {
ws->rendernode_fd = open(drmGetRenderDeviceNameFromFd(ws->fd), O_RDWR);
if (ws->rendernode_fd != -1)
return radeon_get_drm_value(ws, request, errname, out);
}
}
if (retval && ws->rendernode_fd == -1) {
if (errname) {
fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
errname, retval);
@@ -164,7 +156,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
drmFreeVersion(version);
/* Get PCI ID. */
if (!radeon_get_drm_value(ws, RADEON_INFO_DEVICE_ID, "PCI ID",
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
&ws->info.pci_id))
return false;
@@ -309,16 +301,16 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.vce_fw_version = 0x00000000;
uint32_t value = RADEON_CS_RING_UVD;
if (radeon_get_drm_value(ws, RADEON_INFO_RING_WORKING,
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
"UVD Ring working", &value)) {
ws->info.ip[AMD_IP_UVD].num_queues = 1;
}
value = RADEON_CS_RING_VCE;
if (radeon_get_drm_value(ws, RADEON_INFO_RING_WORKING,
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
NULL, &value) && value) {
if (radeon_get_drm_value(ws, RADEON_INFO_VCE_FW_VERSION,
if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
"VCE FW version", &value)) {
ws->info.vce_fw_version = value;
ws->info.ip[AMD_IP_VCE].num_queues = 1;
@@ -336,12 +328,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
* aren't set.
*/
ws->info.has_userptr =
drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_GEM_USERPTR,
drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
&args, sizeof(args)) == -EACCES;
}
/* Get GEM info. */
retval = drmCommandWriteRead(radeon_drm_winsys_fd(ws), DRM_RADEON_GEM_INFO,
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
if (retval) {
fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
@@ -365,7 +357,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.max_heap_size_kb = MIN2(ws->info.max_heap_size_kb, 4 * 1024 * 1024); /* 4 GB */
/* Get max clock frequency info and convert it to MHz */
radeon_get_drm_value(ws, RADEON_INFO_MAX_SCLK, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
&ws->info.max_gpu_freq_mhz);
ws->info.max_gpu_freq_mhz /= 1000;
@@ -373,12 +365,12 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Generation-specific queries. */
if (ws->gen == DRV_R300) {
if (!radeon_get_drm_value(ws, RADEON_INFO_NUM_GB_PIPES,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
"GB pipe count",
&ws->info.r300_num_gb_pipes))
return false;
if (!radeon_get_drm_value(ws, RADEON_INFO_NUM_Z_PIPES,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
"Z pipe count",
&ws->info.r300_num_z_pipes))
return false;
@@ -386,16 +378,16 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
else if (ws->gen >= DRV_R600) {
uint32_t tiling_config = 0;
if (!radeon_get_drm_value(ws, RADEON_INFO_NUM_BACKENDS,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
"num backends",
&ws->info.max_render_backends))
return false;
/* get the GPU counter frequency, failure is not fatal */
radeon_get_drm_value(ws, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
&ws->info.clock_crystal_freq);
radeon_get_drm_value(ws, RADEON_INFO_TILING_CONFIG, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
&tiling_config);
ws->info.r600_num_banks =
@@ -412,7 +404,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.pipe_interleave_bytes =
ws->info.gfx_level >= EVERGREEN ? 512 : 256;
radeon_get_drm_value(ws, RADEON_INFO_NUM_TILE_PIPES, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
&ws->info.num_tile_pipes);
/* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
@@ -423,7 +415,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
ws->info.num_tile_pipes = 8;
if (radeon_get_drm_value(ws, RADEON_INFO_BACKEND_MAP, NULL,
if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
&ws->info.r600_gb_backend_map))
ws->info.r600_gb_backend_map_valid = true;
@@ -436,7 +428,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
if (ws->gen >= DRV_SI) {
uint32_t mask;
radeon_get_drm_value(ws, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL, &mask);
radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL, &mask);
ws->info.enabled_rb_mask = mask;
}
@@ -445,13 +437,13 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
uint32_t ib_vm_max_size;
ws->info.r600_has_virtual_memory = true;
if (!radeon_get_drm_value(ws, RADEON_INFO_VA_START, NULL,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
&ws->va_start))
ws->info.r600_has_virtual_memory = false;
if (!radeon_get_drm_value(ws, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
&ib_vm_max_size))
ws->info.r600_has_virtual_memory = false;
radeon_get_drm_value(ws, RADEON_INFO_VA_UNMAP_WORKING, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
&ws->va_unmap_working);
if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
@@ -461,15 +453,15 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Get max pipes, this is only needed for compute shaders. All evergreen+
* chips have at least 2 pipes, so we use 2 as a default. */
ws->info.r600_max_quad_pipes = 2;
radeon_get_drm_value(ws, RADEON_INFO_MAX_PIPES, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
&ws->info.r600_max_quad_pipes);
/* All GPUs have at least one compute unit */
ws->info.num_cu = 1;
radeon_get_drm_value(ws, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
&ws->info.num_cu);
radeon_get_drm_value(ws, RADEON_INFO_MAX_SE, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
&ws->info.max_se);
switch (ws->info.family) {
@@ -519,7 +511,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.num_se = ws->info.max_se;
radeon_get_drm_value(ws, RADEON_INFO_MAX_SH_PER_SE, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
&ws->info.max_sa_per_se);
if (ws->gen == DRV_SI) {
ws->info.max_good_cu_per_sa =
@@ -527,7 +519,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
(ws->info.max_se * ws->info.max_sa_per_se);
}
radeon_get_drm_value(ws, RADEON_INFO_ACCEL_WORKING2, NULL,
radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
&ws->accel_working2);
if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
@@ -538,7 +530,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
}
if (ws->info.gfx_level == GFX7) {
if (!radeon_get_drm_value(ws, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
ws->info.cik_macrotile_mode_array)) {
fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
return false;
@@ -546,7 +538,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
}
if (ws->info.gfx_level >= GFX6) {
if (!radeon_get_drm_value(ws, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
ws->info.si_tile_mode_array)) {
fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
return false;
@@ -684,8 +676,6 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
if (ws->fd >= 0)
close(ws->fd);
if (ws->rendernode_fd >= 0)
close(ws->rendernode_fd);
FREE(rws);
}
@@ -721,7 +711,7 @@ uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
{
uint64_t retval = 0;
radeon_get_drm_value(ws, RADEON_INFO_GPU_RESET_COUNTER,
radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
"gpu-reset-counter", (uint32_t*)&retval);
return retval;
}
@@ -751,7 +741,7 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
return 0;
}
radeon_get_drm_value(ws, RADEON_INFO_TIMESTAMP, "timestamp",
radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
(uint32_t*)&retval);
return retval;
case RADEON_NUM_GFX_IBS:
@@ -759,7 +749,7 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
case RADEON_NUM_SDMA_IBS:
return ws->num_sdma_IBs;
case RADEON_NUM_BYTES_MOVED:
radeon_get_drm_value(ws, RADEON_INFO_NUM_BYTES_MOVED,
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
"num-bytes-moved", (uint32_t*)&retval);
return retval;
case RADEON_NUM_EVICTIONS:
@@ -771,23 +761,23 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
case RADEON_SLAB_WASTED_GTT:
return 0; /* unimplemented */
case RADEON_VRAM_USAGE:
radeon_get_drm_value(ws, RADEON_INFO_VRAM_USAGE,
radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
"vram-usage", (uint32_t*)&retval);
return retval;
case RADEON_GTT_USAGE:
radeon_get_drm_value(ws, RADEON_INFO_GTT_USAGE,
radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
"gtt-usage", (uint32_t*)&retval);
return retval;
case RADEON_GPU_TEMPERATURE:
radeon_get_drm_value(ws, RADEON_INFO_CURRENT_GPU_TEMP,
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
"gpu-temp", (uint32_t*)&retval);
return retval;
case RADEON_CURRENT_SCLK:
radeon_get_drm_value(ws, RADEON_INFO_CURRENT_GPU_SCLK,
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
"current-gpu-sclk", (uint32_t*)&retval);
return retval;
case RADEON_CURRENT_MCLK:
radeon_get_drm_value(ws, RADEON_INFO_CURRENT_GPU_MCLK,
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
"current-gpu-mclk", (uint32_t*)&retval);
return retval;
case RADEON_CS_THREAD_TIME:
@@ -806,7 +796,7 @@ static bool radeon_read_registers(struct radeon_winsys *rws,
for (i = 0; i < num_registers; i++) {
uint32_t reg = reg_offset + i*4;
if (!radeon_get_drm_value(ws, RADEON_INFO_READ_REG, NULL, &reg))
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
return false;
out[i] = reg;
}
@@ -865,7 +855,7 @@ radeon_drm_winsys_get_fd(struct radeon_winsys *ws)
{
struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
return radeon_drm_winsys_fd(rws);
return rws->fd;
}
PUBLIC struct radeon_winsys *
@@ -893,7 +883,6 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
}
ws->fd = os_dupfd_cloexec(fd);
ws->rendernode_fd = -1;
if (!do_winsys_init(ws))
goto fail1;
@@ -926,7 +915,7 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
}
if (ws->gen >= DRV_R600) {
ws->surf_man = radeon_surface_manager_new(radeon_drm_winsys_fd(ws));
ws->surf_man = radeon_surface_manager_new(ws->fd);
if (!ws->surf_man)
goto fail_slab;
}
@@ -1016,8 +1005,6 @@ fail1:
radeon_surface_manager_free(ws->surf_man);
if (ws->fd >= 0)
close(ws->fd);
if (ws->rendernode_fd >= 0)
close(ws->rendernode_fd);
FREE(ws);
return NULL;

7
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
View File

@@ -39,7 +39,6 @@ struct radeon_drm_winsys {
struct pb_slabs bo_slabs;
int fd; /* DRM file descriptor */
int rendernode_fd; /* valid only when import handles must do an intermediate export -> import onto DRM fd */
int num_cs; /* The number of command streams created. */
uint64_t allocated_vram;
uint64_t allocated_gtt;
@@ -90,12 +89,6 @@ static inline struct radeon_drm_winsys *radeon_drm_winsys(struct radeon_winsys *
return (struct radeon_drm_winsys*)base;
}
ALWAYS_INLINE static int
radeon_drm_winsys_fd(const struct radeon_drm_winsys *ws)
{
return ws->rendernode_fd == -1 ? ws->fd : ws->rendernode_fd;
}
uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws);
void radeon_surface_init_functions(struct radeon_drm_winsys *ws);