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intel/fs: bump max SIMD size for A64 atomics with LSC

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>.
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
This commit is contained in:
Lionel Landwerlin
2022-08-01 18:12:45 +03:00
committed by Marge Bot
parent 407f2beb97
commit f242c9af76
1 changed files with 1 additions and 1 deletions
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src/intel/compiler/brw_fs.cpp
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@@ -5047,7 +5047,7 @@ get_lowered_simd_width(const struct brw_compiler *compiler,
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL:
return 8;
return devinfo->has_lsc ? MIN2(16, inst->exec_size) : 8;
case SHADER_OPCODE_URB_READ_LOGICAL:
case SHADER_OPCODE_URB_WRITE_LOGICAL: