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radv: remove radv_graphics_pipeline::last_vertex_attrib_bit

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Use the VS shader info instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22192>
This commit is contained in:
Samuel Pitoiset
2023-03-29 15:53:06 +02:00
committed by Marge Bot
parent 99bca4cb50
commit f224e9f1a5
3 changed files with 2 additions and 4 deletions
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2
src/amd/vulkan/radv_cmd_buffer.c
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@@ -3660,7 +3660,7 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
struct radv_device *device = cmd_buffer->device; struct radv_device *device = cmd_buffer->device;
unsigned num_attributes = pipeline->last_vertex_attrib_bit; unsigned num_attributes = util_last_bit(vs_shader->info.vs.vb_desc_usage_mask);
uint32_t attribute_mask = BITFIELD_MASK(num_attributes); uint32_t attribute_mask = BITFIELD_MASK(num_attributes);
uint32_t instance_rate_inputs = state->instance_rate_inputs & attribute_mask; uint32_t instance_rate_inputs = state->instance_rate_inputs & attribute_mask;

3
src/amd/vulkan/radv_pipeline.c
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@@ -4409,7 +4409,6 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
} }
} }
pipeline->last_vertex_attrib_bit = util_last_bit(vs_info->vs.vb_desc_usage_mask);
if (pipeline->base.shaders[MESA_SHADER_VERTEX]) if (pipeline->base.shaders[MESA_SHADER_VERTEX])
pipeline->next_vertex_stage = MESA_SHADER_VERTEX; pipeline->next_vertex_stage = MESA_SHADER_VERTEX;
else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL]) else if (pipeline->base.shaders[MESA_SHADER_TESS_CTRL])
@@ -4424,7 +4423,7 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
pipeline->can_use_simple_input = false; pipeline->can_use_simple_input = false;
} }
if (vs_info->vs.dynamic_inputs) if (vs_info->vs.dynamic_inputs)
pipeline->vb_desc_usage_mask = BITFIELD_MASK(pipeline->last_vertex_attrib_bit); pipeline->vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(vs_info->vs.vb_desc_usage_mask));
else else
pipeline->vb_desc_usage_mask = vs_info->vs.vb_desc_usage_mask; pipeline->vb_desc_usage_mask = vs_info->vs.vb_desc_usage_mask;
pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16; pipeline->vb_desc_alloc_size = util_bitcount(pipeline->vb_desc_usage_mask) * 16;

1
src/amd/vulkan/radv_private.h
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@@ -2242,7 +2242,6 @@ struct radv_graphics_pipeline {
uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS]; uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
uint32_t vb_desc_usage_mask; uint32_t vb_desc_usage_mask;
uint32_t vb_desc_alloc_size; uint32_t vb_desc_alloc_size;
uint8_t last_vertex_attrib_bit;
uint8_t next_vertex_stage; uint8_t next_vertex_stage;
uint32_t pa_sc_mode_cntl_1; uint32_t pa_sc_mode_cntl_1;
uint32_t db_render_control; uint32_t db_render_control;