nir: Collect if shader uses cross-invocation or indirect I/O.
The following new fields are added to tess shader info: * `tcs_cross_invocation_inputs_read` * `tcs_cross_invocation_outputs_read` These are I/O masks that are a subset of inputs_read and outputs_read and they contain which per-vertex inputs and outputs are read cross-invocation. Additionall, the following new fields are added to shader_info: * `inputs_read_indirectly` * `outputs_accessed_indirectly` * `patch_inputs_read_indirectly` * `patch_outputs_accessed_indirectly` These new fields can be used for optimizing TCS in a back-end compiler. If you can be sure that the TCS doesn't use cross-invocation inputs or outputs, you can choose a different strategy for storing VS and TCS outputs. However, such optimizations might need to be disabled when the inputs/outputs are accessed indirectly due to backend limitations, so this information is also collected. Example: RADV currently has to store all VS and TCS outputs in LDS, but for shaders when only inputs and/or outputs belonging to the current invocation ID are used, it could skip storing these in LDS entirely. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4165>
This commit is contained in:
@@ -22,11 +22,54 @@
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*/
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*/
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#include "nir.h"
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#include "nir.h"
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#include "nir_deref.h"
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#include "main/menums.h"
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#include "main/menums.h"
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static void
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get_deref_info(nir_shader *shader, nir_variable *var, nir_deref_instr *deref,
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bool *cross_invocation, bool *indirect)
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{
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*cross_invocation = false;
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*indirect = false;
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const bool per_vertex = nir_is_per_vertex_io(var, shader->info.stage);
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nir_deref_path path;
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nir_deref_path_init(&path, deref, NULL);
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assert(path.path[0]->deref_type == nir_deref_type_var);
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nir_deref_instr **p = &path.path[1];
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/* Vertex index is the outermost array index. */
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if (per_vertex) {
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assert((*p)->deref_type == nir_deref_type_array);
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nir_instr *vertex_index_instr = (*p)->arr.index.ssa->parent_instr;
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*cross_invocation =
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vertex_index_instr->type != nir_instr_type_intrinsic ||
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nir_instr_as_intrinsic(vertex_index_instr)->intrinsic !=
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nir_intrinsic_load_invocation_id;
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p++;
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}
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/* We always lower indirect dereferences for "compact" array vars. */
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if (!path.path[0]->var->data.compact) {
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/* Non-compact array vars: find out if they are indirect. */
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for (; *p; p++) {
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if ((*p)->deref_type == nir_deref_type_array) {
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*indirect |= !nir_src_is_const((*p)->arr.index);
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} else if ((*p)->deref_type == nir_deref_type_struct) {
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/* Struct indices are always constant. */
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} else {
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unreachable("Unsupported deref type");
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}
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}
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}
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nir_deref_path_finish(&path);
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}
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static void
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static void
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set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
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set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
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bool is_output_read)
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nir_deref_instr *deref, bool is_output_read)
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{
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{
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for (int i = 0; i < len; i++) {
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for (int i = 0; i < len; i++) {
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assert(var->data.location != -1);
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assert(var->data.location != -1);
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@@ -48,11 +91,23 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
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bitfield = BITFIELD64_BIT(idx);
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bitfield = BITFIELD64_BIT(idx);
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}
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}
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bool cross_invocation;
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bool indirect;
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get_deref_info(shader, var, deref, &cross_invocation, &indirect);
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if (var->data.mode == nir_var_shader_in) {
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if (var->data.mode == nir_var_shader_in) {
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if (is_patch_generic)
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if (is_patch_generic) {
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shader->info.patch_inputs_read |= bitfield;
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shader->info.patch_inputs_read |= bitfield;
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else
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if (indirect)
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shader->info.patch_inputs_read_indirectly |= bitfield;
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} else {
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shader->info.inputs_read |= bitfield;
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shader->info.inputs_read |= bitfield;
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if (indirect)
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shader->info.inputs_read_indirectly |= bitfield;
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}
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if (cross_invocation)
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shader->info.tess.tcs_cross_invocation_inputs_read |= bitfield;
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if (shader->info.stage == MESA_SHADER_FRAGMENT) {
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if (shader->info.stage == MESA_SHADER_FRAGMENT) {
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shader->info.fs.uses_sample_qualifier |= var->data.sample;
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shader->info.fs.uses_sample_qualifier |= var->data.sample;
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@@ -62,16 +117,27 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
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if (is_output_read) {
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if (is_output_read) {
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if (is_patch_generic) {
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if (is_patch_generic) {
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shader->info.patch_outputs_read |= bitfield;
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shader->info.patch_outputs_read |= bitfield;
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if (indirect)
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shader->info.patch_outputs_accessed_indirectly |= bitfield;
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} else {
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} else {
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shader->info.outputs_read |= bitfield;
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shader->info.outputs_read |= bitfield;
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if (indirect)
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shader->info.outputs_accessed_indirectly |= bitfield;
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}
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}
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if (cross_invocation)
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shader->info.tess.tcs_cross_invocation_outputs_read |= bitfield;
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} else {
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} else {
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if (is_patch_generic) {
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if (is_patch_generic) {
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shader->info.patch_outputs_written |= bitfield;
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shader->info.patch_outputs_written |= bitfield;
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} else if (!var->data.read_only) {
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if (indirect)
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shader->info.outputs_written |= bitfield;
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shader->info.patch_outputs_accessed_indirectly |= bitfield;
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}
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} else if (!var->data.read_only) {
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}
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shader->info.outputs_written |= bitfield;
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if (indirect)
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shader->info.outputs_accessed_indirectly |= bitfield;
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}
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}
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if (var->data.fb_fetch_output)
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if (var->data.fb_fetch_output)
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@@ -85,7 +151,8 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
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* represents a shader input or output.
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* represents a shader input or output.
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*/
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*/
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static void
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static void
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mark_whole_variable(nir_shader *shader, nir_variable *var, bool is_output_read)
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mark_whole_variable(nir_shader *shader, nir_variable *var,
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nir_deref_instr *deref, bool is_output_read)
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{
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{
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const struct glsl_type *type = var->type;
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const struct glsl_type *type = var->type;
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@@ -98,7 +165,7 @@ mark_whole_variable(nir_shader *shader, nir_variable *var, bool is_output_read)
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var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
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var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
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: glsl_count_attribute_slots(type, false);
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: glsl_count_attribute_slots(type, false);
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set_io_mask(shader, var, 0, slots, is_output_read);
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set_io_mask(shader, var, 0, slots, deref, is_output_read);
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}
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}
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static unsigned
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static unsigned
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@@ -193,7 +260,7 @@ try_mask_partial_io(nir_shader *shader, nir_variable *var,
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return false;
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return false;
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}
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}
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set_io_mask(shader, var, offset, elem_width, is_output_read);
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set_io_mask(shader, var, offset, elem_width, deref, is_output_read);
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return true;
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return true;
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}
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}
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@@ -228,7 +295,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
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is_output_read = true;
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is_output_read = true;
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if (!try_mask_partial_io(shader, var, deref, is_output_read))
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if (!try_mask_partial_io(shader, var, deref, is_output_read))
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mark_whole_variable(shader, var, is_output_read);
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mark_whole_variable(shader, var, deref, is_output_read);
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/* We need to track which input_reads bits correspond to a
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/* We need to track which input_reads bits correspond to a
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* dvec3/dvec4 input attribute */
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* dvec3/dvec4 input attribute */
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@@ -462,6 +529,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
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shader->info.num_textures = 0;
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shader->info.num_textures = 0;
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shader->info.num_images = 0;
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shader->info.num_images = 0;
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shader->info.last_msaa_image = -1;
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shader->info.last_msaa_image = -1;
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nir_foreach_variable(var, &shader->uniforms) {
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nir_foreach_variable(var, &shader->uniforms) {
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/* Bindless textures and images don't use non-bindless slots. */
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/* Bindless textures and images don't use non-bindless slots. */
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if (var->data.bindless)
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if (var->data.bindless)
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@@ -483,6 +551,11 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
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shader->info.patch_inputs_read = 0;
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shader->info.patch_inputs_read = 0;
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shader->info.patch_outputs_written = 0;
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shader->info.patch_outputs_written = 0;
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shader->info.system_values_read = 0;
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shader->info.system_values_read = 0;
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shader->info.inputs_read_indirectly = 0;
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shader->info.outputs_accessed_indirectly = 0;
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shader->info.patch_inputs_read_indirectly = 0;
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shader->info.patch_outputs_accessed_indirectly = 0;
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if (shader->info.stage == MESA_SHADER_VERTEX) {
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if (shader->info.stage == MESA_SHADER_VERTEX) {
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shader->info.vs.double_inputs = 0;
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shader->info.vs.double_inputs = 0;
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}
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}
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@@ -492,6 +565,11 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
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shader->info.fs.uses_demote = false;
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shader->info.fs.uses_demote = false;
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shader->info.fs.needs_helper_invocations = false;
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shader->info.fs.needs_helper_invocations = false;
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}
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}
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if (shader->info.stage == MESA_SHADER_TESS_CTRL) {
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shader->info.tess.tcs_cross_invocation_inputs_read = 0;
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shader->info.tess.tcs_cross_invocation_outputs_read = 0;
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}
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shader->info.writes_memory = shader->info.has_transform_feedback_varyings;
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shader->info.writes_memory = shader->info.has_transform_feedback_varyings;
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void *dead_ctx = ralloc_context(NULL);
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void *dead_ctx = ralloc_context(NULL);
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@@ -134,6 +134,15 @@ typedef struct shader_info {
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/* Which patch outputs are read */
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/* Which patch outputs are read */
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uint32_t patch_outputs_read;
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uint32_t patch_outputs_read;
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/* Which inputs are read indirectly (subset of inputs_read) */
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uint64_t inputs_read_indirectly;
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/* Which outputs are read or written indirectly */
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uint64_t outputs_accessed_indirectly;
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/* Which patch inputs are read indirectly (subset of patch_inputs_read) */
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uint64_t patch_inputs_read_indirectly;
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/* Which patch outputs are read or written indirectly */
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uint64_t patch_outputs_accessed_indirectly;
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/** Bitfield of which textures are used */
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/** Bitfield of which textures are used */
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uint32_t textures_used;
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uint32_t textures_used;
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@@ -321,6 +330,16 @@ typedef struct shader_info {
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uint8_t tcs_vertices_out;
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uint8_t tcs_vertices_out;
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enum gl_tess_spacing spacing:2;
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enum gl_tess_spacing spacing:2;
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/* Bit mask of TCS per-vertex inputs (VS outputs) that are used
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* with a vertex index that is NOT the invocation id
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*/
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uint64_t tcs_cross_invocation_inputs_read;
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/* Bit mask of TCS per-vertex outputs that are used
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* with a vertex index that is NOT the invocation id
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*/
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uint64_t tcs_cross_invocation_outputs_read;
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/** Is the vertex order counterclockwise? */
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/** Is the vertex order counterclockwise? */
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bool ccw:1;
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bool ccw:1;
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bool point_mode:1;
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bool point_mode:1;
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