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Revert "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"

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This reverts commit f6d87ec8a9.

It breaks RADV.

Fixes: f6d87ec8a9 "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4864>
This commit is contained in:
Marek Olšák
2020-05-02 16:01:44 -04:00
committed by Marge Bot
parent ee8f60da19
commit f1a40a26a9
4 changed files with 22 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/amd/common/ac_surface.c
View File

@@ -651,8 +651,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.flags.cube = config->is_cube; AddrSurfInfoIn.flags.cube = config->is_cube;
AddrSurfInfoIn.flags.display = get_display_flag(config, surf); AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1; AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
AddrSurfInfoIn.flags.tcCompatible = info->chip_class >= GFX8 && AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
AddrSurfInfoIn.flags.depth;
/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
* requested, because TC-compatible HTILE requires 2D tiling. * requested, because TC-compatible HTILE requires 2D tiling.
@@ -773,7 +772,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->htile_size = 0; surf->htile_size = 0;
surf->htile_slice_size = 0; surf->htile_slice_size = 0;
surf->htile_alignment = 1; surf->htile_alignment = 1;
surf->tc_compatible_htile_allowed = AddrSurfInfoIn.flags.tcCompatible;
const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) && const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
!(surf->flags & RADEON_SURF_ZBUFFER); !(surf->flags & RADEON_SURF_ZBUFFER);
@@ -790,11 +788,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
if (level > 0) if (level > 0)
continue; continue;
if (!AddrSurfInfoOut.tcCompatible) if (!AddrSurfInfoOut.tcCompatible) {
AddrSurfInfoIn.flags.tcCompatible = 0; AddrSurfInfoIn.flags.tcCompatible = 0;
surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
if (!AddrSurfInfoOut.tcCompatible || !surf->htile_size) }
surf->tc_compatible_htile_allowed = false;
if (AddrSurfInfoIn.flags.matchStencilTileCfg) { if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
AddrSurfInfoIn.flags.matchStencilTileCfg = 0; AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
@@ -940,7 +937,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
* TC-compatible HTILE even for levels where it's disabled by DB. * TC-compatible HTILE even for levels where it's disabled by DB.
*/ */
if (surf->htile_size && config->info.levels > 1 && if (surf->htile_size && config->info.levels > 1 &&
surf->tc_compatible_htile_allowed) { surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
/* MSAA can't occur with levels > 1, so ignore the sample count. */ /* MSAA can't occur with levels > 1, so ignore the sample count. */
const unsigned total_pixels = surf->surf_size / surf->bpe; const unsigned total_pixels = surf->surf_size / surf->bpe;
const unsigned htile_block_size = 8 * 8; const unsigned htile_block_size = 8 * 8;
@@ -1572,12 +1569,14 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.bpp = surf->bpe * 8; AddrSurfInfoIn.bpp = surf->bpe * 8;
} }
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.color = is_color_surface &&
!(surf->flags & RADEON_SURF_NO_RENDER_TARGET); !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.display = get_display_flag(config, surf); AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
/* flags.texture currently refers to TC-compatible HTILE */ /* flags.texture currently refers to TC-compatible HTILE */
AddrSurfInfoIn.flags.texture = 1; AddrSurfInfoIn.flags.texture = is_color_surface ||
surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
AddrSurfInfoIn.flags.opt4space = 1; AddrSurfInfoIn.flags.opt4space = 1;
AddrSurfInfoIn.numMipLevels = config->info.levels; AddrSurfInfoIn.numMipLevels = config->info.levels;
@@ -1717,7 +1716,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
} }
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR; surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
surf->tc_compatible_htile_allowed = surf->htile_size != 0;
/* Query whether the surface is displayable. */ /* Query whether the surface is displayable. */
/* This is only useful for surfaces that are allocated without SCANOUT. */ /* This is only useful for surfaces that are allocated without SCANOUT. */

3
src/amd/common/ac_surface.h
View File

@@ -67,7 +67,7 @@ enum radeon_micro_mode {
/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
#define RADEON_SURF_FMASK (1 << 21) #define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_DISABLE_DCC (1 << 22)
/* gap */ #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_IMPORTED (1 << 24) #define RADEON_SURF_IMPORTED (1 << 24)
/* gap */ /* gap */
#define RADEON_SURF_SHAREABLE (1 << 26) #define RADEON_SURF_SHAREABLE (1 << 26)
@@ -198,7 +198,6 @@ struct radeon_surf {
unsigned has_stencil:1; unsigned has_stencil:1;
/* This might be true even if micro_tile_mode isn't displayable or rotated. */ /* This might be true even if micro_tile_mode isn't displayable or rotated. */
unsigned is_displayable:1; unsigned is_displayable:1;
unsigned tc_compatible_htile_allowed:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */ /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3; unsigned micro_tile_mode:3;
uint32_t flags; uint32_t flags;

14
src/amd/vulkan/radv_image.c
View File

@@ -437,8 +437,11 @@ radv_init_surface(struct radv_device *device,
unreachable("unhandled image type"); unreachable("unhandled image type");
} }
if (is_depth) if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER; surface->flags |= RADEON_SURF_ZBUFFER;
if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
if (is_stencil) if (is_stencil)
surface->flags |= RADEON_SURF_SBUFFER; surface->flags |= RADEON_SURF_SBUFFER;
@@ -1348,8 +1351,6 @@ static void radv_image_disable_htile(struct radv_image *image)
{ {
for (unsigned i = 0; i < image->plane_count; ++i) for (unsigned i = 0; i < image->plane_count; ++i)
image->planes[i].surface.htile_size = 0; image->planes[i].surface.htile_size = 0;
image->tc_compatible_htile = false;
} }
VkResult VkResult
@@ -1421,8 +1422,7 @@ radv_image_create_layout(struct radv_device *device,
/* Otherwise, try to enable HTILE for depth surfaces. */ /* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) && if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) { !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
if (!image->planes[0].surface.tc_compatible_htile_allowed) image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
image->tc_compatible_htile = false;
radv_image_alloc_htile(device, image); radv_image_alloc_htile(device, image);
} else { } else {
radv_image_disable_htile(image); radv_image_disable_htile(image);
@@ -1500,10 +1500,6 @@ radv_image_create(VkDevice _device,
image->info.surf_index = &device->image_mrt_offset_counter; image->info.surf_index = &device->image_mrt_offset_counter;
} }
image->tc_compatible_htile =
radv_use_tc_compat_htile_for_image(device, create_info->vk_info,
image->vk_format);
for (unsigned plane = 0; plane < image->plane_count; ++plane) { for (unsigned plane = 0; plane < image->plane_count; ++plane) {
radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format); radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
} }

14
src/gallium/drivers/radeonsi/si_texture.c
View File

@@ -241,6 +241,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
*/ */
if (sscreen->info.chip_class == GFX8) if (sscreen->info.chip_class == GFX8)
bpe = 4; bpe = 4;
flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
} }
if (is_stencil) if (is_stencil)
@@ -1186,8 +1188,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
const struct radeon_surf *surface, const struct radeon_surf *surface,
const struct si_texture *plane0, const struct si_texture *plane0,
struct pb_buffer *imported_buf, uint64_t offset, struct pb_buffer *imported_buf, uint64_t offset,
uint64_t alloc_size, unsigned alignment, uint64_t alloc_size, unsigned alignment)
bool tc_compatible_htile)
{ {
struct si_texture *tex; struct si_texture *tex;
struct si_resource *resource; struct si_resource *resource;
@@ -1206,8 +1207,8 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
/* don't include stencil-only formats which we don't support for rendering */ /* don't include stencil-only formats which we don't support for rendering */
tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format)); tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
tex->surface = *surface; tex->surface = *surface;
tex->tc_compatible_htile = tex->surface.tc_compatible_htile_allowed && tex->tc_compatible_htile =
tc_compatible_htile; tex->surface.htile_size != 0 && (tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
/* TC-compatible HTILE: /* TC-compatible HTILE:
* - GFX8 only supports Z32_FLOAT. * - GFX8 only supports Z32_FLOAT.
@@ -1568,8 +1569,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
for (unsigned i = 0; i < num_planes; i++) { for (unsigned i = 0; i < num_planes; i++) {
struct si_texture *tex = struct si_texture *tex =
si_texture_create_object(screen, &plane_templ[i], &surface[i], plane0, NULL, si_texture_create_object(screen, &plane_templ[i], &surface[i], plane0, NULL,
plane_offset[i], total_size, max_alignment, plane_offset[i], total_size, max_alignment);
tc_compatible_htile);
if (!tex) { if (!tex) {
si_texture_reference(&plane0, NULL); si_texture_reference(&plane0, NULL);
return NULL; return NULL;
@@ -1641,7 +1641,7 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
if (r) if (r)
return NULL; return NULL;
tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, offset, 0, 0, false); tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf, offset, 0, 0);
if (!tex) if (!tex)
return NULL; return NULL;