From f199b7188b41b48636e34cfd1e014778d53459a1 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 13 Mar 2020 15:43:16 +0000 Subject: [PATCH] nir/load_store_vectorize: add data as callback args Signed-off-by: Rhys Perry Reviewed-by: Jason Ekstrand Part-of: --- src/amd/vulkan/radv_pipeline.c | 3 ++- src/compiler/nir/nir.h | 4 +++- src/compiler/nir/nir_opt_load_store_vectorize.c | 3 ++- src/compiler/nir/tests/load_store_vectorizer_tests.cpp | 6 ++++-- src/freedreno/ir3/ir3_nir.c | 3 ++- src/gallium/auxiliary/nir/nir_to_tgsi.c | 3 ++- src/intel/compiler/brw_nir.c | 3 ++- 7 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 83ecd8137bd..a4966722b91 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3032,7 +3032,8 @@ static bool mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, - nir_intrinsic_instr *low, nir_intrinsic_instr *high) + nir_intrinsic_instr *low, nir_intrinsic_instr *high, + void *data) { if (num_components > 4) return false; diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index aa77e7b2592..04e54d637cf 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -5010,12 +5010,14 @@ typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, - nir_intrinsic_instr *low, nir_intrinsic_instr *high); + nir_intrinsic_instr *low, nir_intrinsic_instr *high, + void *data); typedef struct { nir_should_vectorize_mem_func callback; nir_variable_mode modes; nir_variable_mode robust_modes; + void *cb_data; } nir_load_store_vectorize_options; bool nir_opt_load_store_vectorize(nir_shader *shader, const nir_load_store_vectorize_options *options); diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c b/src/compiler/nir/nir_opt_load_store_vectorize.c index 979197c2604..fc06336408c 100644 --- a/src/compiler/nir/nir_opt_load_store_vectorize.c +++ b/src/compiler/nir/nir_opt_load_store_vectorize.c @@ -649,7 +649,8 @@ new_bitsize_acceptable(struct vectorize_ctx *ctx, unsigned new_bit_size, if (!ctx->options->callback(low->align_mul, low->align_offset, new_bit_size, new_num_components, - low->intrin, high->intrin)) + low->intrin, high->intrin, + ctx->options->cb_data)) return false; if (low->is_store) { diff --git a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp index f06f8558b32..5a841a2ceb7 100644 --- a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp +++ b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp @@ -73,7 +73,8 @@ protected: static bool mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, - nir_intrinsic_instr *low, nir_intrinsic_instr *high); + nir_intrinsic_instr *low, nir_intrinsic_instr *high, + void *data); static void shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align); std::string swizzle(nir_alu_instr *instr, int src); @@ -359,7 +360,8 @@ bool nir_load_store_vectorize_test::test_alu_def( bool nir_load_store_vectorize_test::mem_vectorize_callback( unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, - nir_intrinsic_instr *low, nir_intrinsic_instr *high) + nir_intrinsic_instr *low, nir_intrinsic_instr *high, + void *data) { /* Calculate a simple alignment, like how nir_intrinsic_align() does. */ uint32_t align = align_mul; diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index 328ea26baab..d16f036c4ef 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -150,7 +150,8 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, nir_intrinsic_instr *low, - nir_intrinsic_instr *high) + nir_intrinsic_instr *high, + void *data) { assert(bit_size >= 8); if (bit_size != 32) diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 5bff29a31c8..01f69df1ac8 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -2204,7 +2204,8 @@ ntt_should_vectorize_instr(const nir_instr *instr, void *data) static bool ntt_should_vectorize_io(unsigned align, unsigned bit_size, unsigned num_components, unsigned high_offset, - nir_intrinsic_instr *low, nir_intrinsic_instr *high) + nir_intrinsic_instr *low, nir_intrinsic_instr *high, + void *data) { if (bit_size != 32) return false; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 97f20fef47b..0b319d6afac 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -969,7 +969,8 @@ brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components, nir_intrinsic_instr *low, - nir_intrinsic_instr *high) + nir_intrinsic_instr *high, + void *data) { /* Don't combine things to generate 64-bit loads/stores. We have to split * those back into 32-bit ones anyway and UBO loads aren't split in NIR so