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radeonsi/gfx11: use a better workaround for the export conflict bug

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This is recommended for better performance.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17864>
This commit is contained in:
Marek Olšák
2022-07-11 02:24:14 -04:00
committed by Marge Bot
parent 2ed9eb1b63
commit f129db911b
4 changed files with 17 additions and 3 deletions
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2
src/amd/common/ac_gpu_info.c
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@@ -1134,6 +1134,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
(info->gfx_level == GFX9 &&
info->me_fw_feature >= 52);
info->has_export_conflict_bug = info->gfx_level == GFX11;
/* Get the number of good compute units. */
info->num_cu = 0;
for (i = 0; i < info->max_se; i++) {

1
src/amd/common/ac_gpu_info.h
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@@ -114,6 +114,7 @@ struct radeon_info {
bool has_sqtt_auto_flush_mode_bug;
bool never_send_perfcounter_stop;
bool discardable_allows_big_page;
bool has_export_conflict_bug;
/* Display features. */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */

14
src/gallium/drivers/radeonsi/si_state.c
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@@ -636,8 +636,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
/* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE ||
(sctx->gfx_level == GFX11 && blend->blend_enable_4bit))
if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE)
color_control |= S_028808_DISABLE_DUAL_QUAD(1);
}
@@ -743,6 +742,10 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state)
sctx->framebuffer.has_dcc_msaa))
si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
if (sctx->screen->info.has_export_conflict_bug &&
old_blend->blend_enable_4bit != blend->blend_enable_4bit)
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (old_blend->cb_target_mask != blend->cb_target_mask ||
old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
old_blend->alpha_to_one != blend->alpha_to_one ||
@@ -1592,6 +1595,13 @@ static void si_emit_db_render_state(struct si_context *sctx)
if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
if (sctx->screen->info.has_export_conflict_bug &&
sctx->queued.named.blend->blend_enable_4bit &&
si_get_num_coverage_samples(sctx) == 1) {
db_shader_control |= S_02880C_OVERRIDE_INTRINSIC_RATE_ENABLE(1) |
S_02880C_OVERRIDE_INTRINSIC_RATE(2);
}
radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
db_shader_control);

3
src/gallium/drivers/radeonsi/si_state_draw.cpp
View File

@@ -289,7 +289,8 @@ static bool si_update_shaders(struct si_context *sctx)
if (GFX_VERSION >= GFX10 && sctx->screen->use_ngg_culling)
si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
if (GFX_VERSION == GFX6)
if (GFX_VERSION == GFX6 ||
(GFX_VERSION == GFX11 && sctx->screen->info.has_export_conflict_bug))
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (sctx->framebuffer.nr_samples <= 1)