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gallium: remove PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE

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Reviewed-by: Brian Paul <brianp@vmware.com>
This commit is contained in:
Marek Olšák
2013-01-14 06:58:52 +01:00
parent cabe4fbb85
commit f04dd3d003
13 changed files with 1 additions and 19 deletions
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3
src/gallium/docs/source/context.rst
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@@ -207,8 +207,7 @@ the framebuffer to particular RGBA, depth, or stencil values.
Currently, this does not take into account color or stencil write masks (as
used by GL), and always clears the whole surfaces (no scissoring as used by
GL clear or explicit rectangles like d3d9 uses). It can, however, also clear
only depth or stencil in a combined depth/stencil surface, if the driver
supports PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE.
only depth or stencil in a combined depth/stencil surface.
If a surface includes several layers then all layers will be cleared.
``clear_render_target`` clears a single color rendertarget with the specified

2
src/gallium/docs/source/screen.rst
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@@ -61,8 +61,6 @@ The integer capabilities:
* ``PIPE_CAP_INDEP_BLEND_FUNC``: Whether per-rendertarget blend functions are
available. If 0, then the first rendertarget's blend functions affect all
MRTs.
* ``PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE``: Whether clearing only depth or only
stencil in a combined depth-stencil buffer is supported.
* ``PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS``: The maximum number of texture array
layers supported. If 0, the array textures are not supported at all and
the ARRAY texture targets are invalid.

1
src/gallium/drivers/i915/i915_screen.c
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@@ -170,7 +170,6 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
switch (cap) {
/* Supported features (boolean caps). */
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */

2
src/gallium/drivers/llvmpipe/lp_screen.c
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@@ -158,8 +158,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 0;
case PIPE_CAP_PRIMITIVE_RESTART:
return 1;
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
return 1;
case PIPE_CAP_DEPTH_CLIP_DISABLE:
return 0;
case PIPE_CAP_SHADER_STENCIL_EXPORT:

1
src/gallium/drivers/nv30/nv30_screen.c
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@@ -74,7 +74,6 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:

1
src/gallium/drivers/nv50/nv50_screen.c
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@@ -118,7 +118,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
*/
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_POINT_SPRITE:
return 1;
case PIPE_CAP_SM3:

1
src/gallium/drivers/nvc0/nvc0_screen.c
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@@ -94,7 +94,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_POINT_SPRITE:
return 1;
case PIPE_CAP_SM3:

1
src/gallium/drivers/r300/r300_screen.c
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@@ -97,7 +97,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_CONDITIONAL_RENDER:

1
src/gallium/drivers/r600/r600_pipe.c
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@@ -393,7 +393,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:

1
src/gallium/drivers/radeonsi/radeonsi_pipe.c
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@@ -303,7 +303,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:

2
src/gallium/drivers/softpipe/sp_screen.c
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@@ -118,8 +118,6 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 16*4;
case PIPE_CAP_PRIMITIVE_RESTART:
return 1;
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
return 0;
case PIPE_CAP_SHADER_STENCIL_EXPORT:
return 1;
case PIPE_CAP_TGSI_INSTANCEID:

3
src/gallium/drivers/svga/svga_screen.c
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@@ -209,9 +209,6 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
return 0;
case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
return 1;
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
return 1; /* The color outputs of vertex shaders are not clamped */
case PIPE_CAP_VERTEX_COLOR_CLAMPED:

1
src/gallium/include/pipe/p_defines.h
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@@ -457,7 +457,6 @@ enum pipe_cap {
PIPE_CAP_INDEP_BLEND_ENABLE = 33,
/** different blend funcs per rendertarget */
PIPE_CAP_INDEP_BLEND_FUNC = 34,
PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE = 35,
PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS = 36,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT = 37,
PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT = 38,