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intel: Require ISL_AUX_USAGE_STC_CCS for stencil CCS

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Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
This commit is contained in:
Jason Ekstrand
2020-03-10 12:11:43 -05:00
committed by Marge Bot
parent 56e15bf31c
commit f047e504a5
3 changed files with 6 additions and 3 deletions
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3
src/intel/blorp/blorp_genX_exec.h
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@@ -1805,8 +1805,7 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
hzp.DepthBufferResolveEnable = params->depth.enabled;
#if GEN_GEN >= 12
if (params->stencil.enabled) {
assert(params->stencil.aux_usage == ISL_AUX_USAGE_CCS_E ||
params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
assert(params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
hzp.StencilBufferResolveEnable = true;
}
#endif

3
src/intel/isl/isl_emit_depth_stencil.c
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@@ -164,8 +164,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
sb.SurfLOD = info->view->base_level;
sb.MinimumArrayElement = info->view->base_array_layer;
assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
sb.StencilCompressionEnable =
info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E ||
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#elif GEN_GEN >= 8 || GEN_IS_HASWELL

3
src/intel/isl/isl_surface_state.c
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@@ -587,6 +587,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
if (isl_surf_usage_is_depth(info->surf->usage))
assert(isl_aux_usage_has_hiz(info->aux_usage));
if (isl_surf_usage_is_stencil(info->surf->usage))
assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
if (isl_aux_usage_has_hiz(info->aux_usage)) {
/* For Gen8-10, there are some restrictions around sampling from HiZ.
* The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode