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anv: Add initial Haswell support

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This commit is contained in:
Jason Ekstrand
2015-11-17 07:07:02 -08:00
parent 45320f677b
commit f0390bcad6
8 changed files with 171 additions and 77 deletions
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24
src/vulkan/Makefile.am
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@@ -34,6 +34,12 @@ lib_LTLIBRARIES = libvulkan.la
check_LTLIBRARIES = libvulkan-test.la check_LTLIBRARIES = libvulkan-test.la
PER_GEN_LIBS = \
libanv-gen7.la \
libanv-gen75.la
noinst_LTLIBRARIES = $(PER_GEN_LIBS)
# The gallium includes are for the util/u_math.h include from main/macros.h # The gallium includes are for the util/u_math.h include from main/macros.h
AM_CPPFLAGS = \ AM_CPPFLAGS = \
@@ -81,9 +87,6 @@ VULKAN_SOURCES = \
gen8_state.c \ gen8_state.c \
gen8_cmd_buffer.c \ gen8_cmd_buffer.c \
gen8_pipeline.c \ gen8_pipeline.c \
gen7_state.c \
gen7_cmd_buffer.c \
gen7_pipeline.c \
isl.c \ isl.c \
isl_format_layout.c isl_format_layout.c
@@ -92,6 +95,18 @@ BUILT_SOURCES = \
anv_entrypoints.c \ anv_entrypoints.c \
isl_format_layout.c isl_format_layout.c
libanv_gen7_la_SOURCES = \
gen7_cmd_buffer.c \
gen7_pipeline.c \
gen7_state.c
libanv_gen7_la_CFLAGS = $(libvulkan_la_CFLAGS) -DANV_GENx10=70
libanv_gen75_la_SOURCES = \
gen7_cmd_buffer.c \
gen7_pipeline.c \
gen7_state.c
libanv_gen75_la_CFLAGS = $(libvulkan_la_CFLAGS) -DANV_GENx10=75
if HAVE_EGL_PLATFORM_WAYLAND if HAVE_EGL_PLATFORM_WAYLAND
BUILT_SOURCES += \ BUILT_SOURCES += \
wayland-drm-protocol.c \ wayland-drm-protocol.c \
@@ -131,7 +146,8 @@ libvulkan_la_LIBADD = $(WAYLAND_LIBS) -lxcb -lxcb-dri3 \
$(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \
../mesa/libmesa.la \ ../mesa/libmesa.la \
../mesa/drivers/dri/common/libdri_test_stubs.la \ ../mesa/drivers/dri/common/libdri_test_stubs.la \
-lpthread -ldl -lstdc++ -lpthread -ldl -lstdc++ \
$(PER_GEN_LIBS)
# Libvulkan with dummy gem. Used for unit tests. # Libvulkan with dummy gem. Used for unit tests.

8
src/vulkan/anv_device.c
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@@ -83,8 +83,9 @@ anv_physical_device_init(struct anv_physical_device *device,
goto fail; goto fail;
} }
if (device->info->gen == 7 && if (device->info->is_haswell) {
!device->info->is_haswell && !device->info->is_baytrail) { fprintf(stderr, "WARNING: Haswell Vulkan support is incomplete\n");
} else if (device->info->gen == 7 && !device->info->is_baytrail) {
fprintf(stderr, "WARNING: Ivy Bridge Vulkan support is incomplete\n"); fprintf(stderr, "WARNING: Ivy Bridge Vulkan support is incomplete\n");
} else if (device->info->gen == 8 && !device->info->is_cherryview) { } else if (device->info->gen == 8 && !device->info->is_cherryview) {
/* Briadwell is as fully supported as anything */ /* Briadwell is as fully supported as anything */
@@ -1439,6 +1440,9 @@ anv_fill_buffer_surface_state(struct anv_device *device, void *state,
{ {
switch (device->info.gen) { switch (device->info.gen) {
case 7: case 7:
if (device->info.is_haswell)
gen75_fill_buffer_surface_state(state, format, offset, range, stride);
else
gen7_fill_buffer_surface_state(state, format, offset, range, stride); gen7_fill_buffer_surface_state(state, format, offset, range, stride);
break; break;
case 8: case 8:

3
src/vulkan/anv_image.c
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@@ -565,6 +565,9 @@ anv_image_view_init(struct anv_image_view *iview,
switch (device->info.gen) { switch (device->info.gen) {
case 7: case 7:
if (device->info.is_haswell)
gen75_image_view_init(iview, device, pCreateInfo, cmd_buffer);
else
gen7_image_view_init(iview, device, pCreateInfo, cmd_buffer); gen7_image_view_init(iview, device, pCreateInfo, cmd_buffer);
break; break;
case 8: case 8:

6
src/vulkan/anv_pipeline.c
View File

@@ -1087,6 +1087,9 @@ anv_graphics_pipeline_create(
switch (device->info.gen) { switch (device->info.gen) {
case 7: case 7:
if (device->info.is_haswell)
return gen75_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
else
return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
case 8: case 8:
return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline);
@@ -1129,6 +1132,9 @@ static VkResult anv_compute_pipeline_create(
switch (device->info.gen) { switch (device->info.gen) {
case 7: case 7:
if (device->info.is_haswell)
return gen75_compute_pipeline_create(_device, pCreateInfo, pPipeline);
else
return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline); return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline);
case 8: case 8:
return gen8_compute_pipeline_create(_device, pCreateInfo, pPipeline); return gen8_compute_pipeline_create(_device, pCreateInfo, pPipeline);

24
src/vulkan/anv_private.h
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@@ -677,6 +677,11 @@ __gen_combine_address(struct anv_batch *batch, void *location,
.L3CacheabilityControlL3CC = 1, \ .L3CacheabilityControlL3CC = 1, \
} }
#define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \
.LLCeLLCCacheabilityControlLLCCC = 0, \
.L3CacheabilityControlL3CC = 1, \
}
#define GEN8_MOCS { \ #define GEN8_MOCS { \
.MemoryTypeLLCeLLCCacheabilityControl = WB, \ .MemoryTypeLLCeLLCCacheabilityControl = WB, \
.TargetCache = L3DefertoPATforLLCeLLCselection, \ .TargetCache = L3DefertoPATforLLCeLLCselection, \
@@ -1198,6 +1203,12 @@ gen7_graphics_pipeline_create(VkDevice _device,
const struct anv_graphics_pipeline_create_info *extra, const struct anv_graphics_pipeline_create_info *extra,
VkPipeline *pPipeline); VkPipeline *pPipeline);
VkResult
gen75_graphics_pipeline_create(VkDevice _device,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct anv_graphics_pipeline_create_info *extra,
VkPipeline *pPipeline);
VkResult VkResult
gen8_graphics_pipeline_create(VkDevice _device, gen8_graphics_pipeline_create(VkDevice _device,
const VkGraphicsPipelineCreateInfo *pCreateInfo, const VkGraphicsPipelineCreateInfo *pCreateInfo,
@@ -1207,6 +1218,10 @@ VkResult
gen7_compute_pipeline_create(VkDevice _device, gen7_compute_pipeline_create(VkDevice _device,
const VkComputePipelineCreateInfo *pCreateInfo, const VkComputePipelineCreateInfo *pCreateInfo,
VkPipeline *pPipeline); VkPipeline *pPipeline);
VkResult
gen75_compute_pipeline_create(VkDevice _device,
const VkComputePipelineCreateInfo *pCreateInfo,
VkPipeline *pPipeline);
VkResult VkResult
gen8_compute_pipeline_create(VkDevice _device, gen8_compute_pipeline_create(VkDevice _device,
@@ -1363,6 +1378,12 @@ gen7_image_view_init(struct anv_image_view *iview,
const VkImageViewCreateInfo* pCreateInfo, const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer); struct anv_cmd_buffer *cmd_buffer);
void
gen75_image_view_init(struct anv_image_view *iview,
struct anv_device *device,
const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer);
void void
gen8_image_view_init(struct anv_image_view *iview, gen8_image_view_init(struct anv_image_view *iview,
struct anv_device *device, struct anv_device *device,
@@ -1377,6 +1398,9 @@ void anv_fill_buffer_surface_state(struct anv_device *device, void *state,
void gen7_fill_buffer_surface_state(void *state, const struct anv_format *format, void gen7_fill_buffer_surface_state(void *state, const struct anv_format *format,
uint32_t offset, uint32_t range, uint32_t offset, uint32_t range,
uint32_t stride); uint32_t stride);
void gen75_fill_buffer_surface_state(void *state, const struct anv_format *format,
uint32_t offset, uint32_t range,
uint32_t stride);
void gen8_fill_buffer_surface_state(void *state, const struct anv_format *format, void gen8_fill_buffer_surface_state(void *state, const struct anv_format *format,
uint32_t offset, uint32_t range, uint32_t offset, uint32_t range,
uint32_t stride); uint32_t stride);

81
src/vulkan/gen7_cmd_buffer.c
View File

@@ -30,9 +30,10 @@
#include "anv_private.h" #include "anv_private.h"
#include "gen7_pack.h" #include "gen7_pack.h"
#include "gen75_pack.h"
static void static void
gen7_cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer) cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
{ {
static const uint32_t push_constant_opcodes[] = { static const uint32_t push_constant_opcodes[] = {
[VK_SHADER_STAGE_VERTEX] = 21, [VK_SHADER_STAGE_VERTEX] = 21,
@@ -65,9 +66,8 @@ gen7_cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.push_constants_dirty &= ~flushed; cmd_buffer->state.push_constants_dirty &= ~flushed;
} }
GENX_FUNC(GEN7, GEN7) void
void genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
gen7_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
{ {
struct anv_device *device = cmd_buffer->device; struct anv_device *device = cmd_buffer->device;
struct anv_bo *scratch_bo = NULL; struct anv_bo *scratch_bo = NULL;
@@ -198,8 +198,8 @@ flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, VkShaderStage stage)
return VK_SUCCESS; return VK_SUCCESS;
} }
void GENX_FUNC(GEN7, GEN7) void
gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer)
{ {
VkShaderStage s; VkShaderStage s;
VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty & VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
@@ -289,8 +289,8 @@ emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
.ScissorRectPointer = scissor_state.offset); .ScissorRectPointer = scissor_state.offset);
} }
void GENX_FUNC(GEN7, GEN7) void
gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer)
{ {
if (cmd_buffer->state.dynamic.scissor.count > 0) { if (cmd_buffer->state.dynamic.scissor.count > 0) {
emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count, emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
@@ -313,7 +313,12 @@ static const uint32_t vk_to_gen_index_type[] = {
[VK_INDEX_TYPE_UINT32] = INDEX_DWORD, [VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
}; };
void gen7_CmdBindIndexBuffer( static const uint32_t restart_index_for_type[] = {
[VK_INDEX_TYPE_UINT16] = UINT16_MAX,
[VK_INDEX_TYPE_UINT32] = UINT32_MAX,
};
void genX(CmdBindIndexBuffer)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkBuffer _buffer, VkBuffer _buffer,
VkDeviceSize offset, VkDeviceSize offset,
@@ -323,13 +328,15 @@ void gen7_CmdBindIndexBuffer(
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
if (ANV_IS_HASWELL)
cmd_buffer->state.restart_index = restart_index_for_type[indexType];
cmd_buffer->state.gen7.index_buffer = buffer; cmd_buffer->state.gen7.index_buffer = buffer;
cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType]; cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
cmd_buffer->state.gen7.index_offset = offset; cmd_buffer->state.gen7.index_offset = offset;
} }
static VkResult static VkResult
gen7_flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
{ {
struct anv_device *device = cmd_buffer->device; struct anv_device *device = cmd_buffer->device;
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
@@ -366,7 +373,7 @@ gen7_flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
} }
static void static void
gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
{ {
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
VkResult result; VkResult result;
@@ -385,7 +392,7 @@ gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) || if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) { (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
/* FIXME: figure out descriptors for gen7 */ /* FIXME: figure out descriptors for gen7 */
result = gen7_flush_compute_descriptor_set(cmd_buffer); result = flush_compute_descriptor_set(cmd_buffer);
assert(result == VK_SUCCESS); assert(result == VK_SUCCESS);
cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE; cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE;
} }
@@ -394,7 +401,7 @@ gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
} }
static void static void
gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
{ {
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
uint32_t *p; uint32_t *p;
@@ -469,7 +476,7 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer); gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer);
if (cmd_buffer->state.push_constants_dirty) if (cmd_buffer->state.push_constants_dirty)
gen7_cmd_buffer_flush_push_constants(cmd_buffer); cmd_buffer_flush_push_constants(cmd_buffer);
/* We use the gen8 state here because it only contains the additional /* We use the gen8 state here because it only contains the additional
* min/max fields and, since they occur at the end of the packet and * min/max fields and, since they occur at the end of the packet and
@@ -564,6 +571,12 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer; struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
uint32_t offset = cmd_buffer->state.gen7.index_offset; uint32_t offset = cmd_buffer->state.gen7.index_offset;
if (ANV_IS_HASWELL) {
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
.IndexedDrawCutIndexEnable = pipeline->primitive_restart,
.CutIndex = cmd_buffer->state.restart_index);
}
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER, anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER,
.CutIndexEnable = pipeline->primitive_restart, .CutIndexEnable = pipeline->primitive_restart,
.IndexFormat = cmd_buffer->state.gen7.index_type, .IndexFormat = cmd_buffer->state.gen7.index_type,
@@ -576,7 +589,7 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty = 0; cmd_buffer->state.dirty = 0;
} }
void gen7_CmdDraw( void genX(CmdDraw)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
uint32_t vertexCount, uint32_t vertexCount,
uint32_t instanceCount, uint32_t instanceCount,
@@ -586,7 +599,7 @@ void gen7_CmdDraw(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
gen7_cmd_buffer_flush_state(cmd_buffer); cmd_buffer_flush_state(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE, anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
.VertexAccessType = SEQUENTIAL, .VertexAccessType = SEQUENTIAL,
@@ -598,7 +611,7 @@ void gen7_CmdDraw(
.BaseVertexLocation = 0); .BaseVertexLocation = 0);
} }
void gen7_CmdDrawIndexed( void genX(CmdDrawIndexed)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
uint32_t indexCount, uint32_t indexCount,
uint32_t instanceCount, uint32_t instanceCount,
@@ -609,7 +622,7 @@ void gen7_CmdDrawIndexed(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
gen7_cmd_buffer_flush_state(cmd_buffer); cmd_buffer_flush_state(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE, anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE,
.VertexAccessType = RANDOM, .VertexAccessType = RANDOM,
@@ -646,7 +659,7 @@ gen7_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
#define GEN7_3DPRIM_START_INSTANCE 0x243C #define GEN7_3DPRIM_START_INSTANCE 0x243C
#define GEN7_3DPRIM_BASE_VERTEX 0x2440 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
void gen7_CmdDrawIndirect( void genX(CmdDrawIndirect)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkBuffer _buffer, VkBuffer _buffer,
VkDeviceSize offset, VkDeviceSize offset,
@@ -659,7 +672,7 @@ void gen7_CmdDrawIndirect(
struct anv_bo *bo = buffer->bo; struct anv_bo *bo = buffer->bo;
uint32_t bo_offset = buffer->offset + offset; uint32_t bo_offset = buffer->offset + offset;
gen7_cmd_buffer_flush_state(cmd_buffer); cmd_buffer_flush_state(cmd_buffer);
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
@@ -673,7 +686,7 @@ void gen7_CmdDrawIndirect(
.PrimitiveTopologyType = pipeline->topology); .PrimitiveTopologyType = pipeline->topology);
} }
void gen7_CmdDrawIndexedIndirect( void genX(CmdDrawIndexedIndirect)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkBuffer _buffer, VkBuffer _buffer,
VkDeviceSize offset, VkDeviceSize offset,
@@ -686,7 +699,7 @@ void gen7_CmdDrawIndexedIndirect(
struct anv_bo *bo = buffer->bo; struct anv_bo *bo = buffer->bo;
uint32_t bo_offset = buffer->offset + offset; uint32_t bo_offset = buffer->offset + offset;
gen7_cmd_buffer_flush_state(cmd_buffer); cmd_buffer_flush_state(cmd_buffer);
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
@@ -700,7 +713,7 @@ void gen7_CmdDrawIndexedIndirect(
.PrimitiveTopologyType = pipeline->topology); .PrimitiveTopologyType = pipeline->topology);
} }
void gen7_CmdDispatch( void genX(CmdDispatch)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
uint32_t x, uint32_t x,
uint32_t y, uint32_t y,
@@ -710,7 +723,7 @@ void gen7_CmdDispatch(
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data; struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
gen7_cmd_buffer_flush_compute_state(cmd_buffer); cmd_buffer_flush_compute_state(cmd_buffer);
anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER, anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER,
.SIMDSize = prog_data->simd_size / 16, .SIMDSize = prog_data->simd_size / 16,
@@ -730,7 +743,7 @@ void gen7_CmdDispatch(
#define GPGPU_DISPATCHDIMY 0x2504 #define GPGPU_DISPATCHDIMY 0x2504
#define GPGPU_DISPATCHDIMZ 0x2508 #define GPGPU_DISPATCHDIMZ 0x2508
void gen7_CmdDispatchIndirect( void genX(CmdDispatchIndirect)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkBuffer _buffer, VkBuffer _buffer,
VkDeviceSize offset) VkDeviceSize offset)
@@ -742,7 +755,7 @@ void gen7_CmdDispatchIndirect(
struct anv_bo *bo = buffer->bo; struct anv_bo *bo = buffer->bo;
uint32_t bo_offset = buffer->offset + offset; uint32_t bo_offset = buffer->offset + offset;
gen7_cmd_buffer_flush_compute_state(cmd_buffer); cmd_buffer_flush_compute_state(cmd_buffer);
gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4); gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
@@ -760,7 +773,7 @@ void gen7_CmdDispatchIndirect(
anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH); anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH);
} }
void gen7_CmdPipelineBarrier( void genX(CmdPipelineBarrier)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkPipelineStageFlags srcStageMask, VkPipelineStageFlags srcStageMask,
VkPipelineStageFlags destStageMask, VkPipelineStageFlags destStageMask,
@@ -772,7 +785,7 @@ void gen7_CmdPipelineBarrier(
} }
static void static void
gen7_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
{ {
const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct anv_image_view *iview = const struct anv_image_view *iview =
@@ -854,14 +867,14 @@ gen7_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS); anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS);
} }
void GENX_FUNC(GEN7, GEN7) void
gen7_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, genX(cmd_buffer_begin_subpass)(struct anv_cmd_buffer *cmd_buffer,
struct anv_subpass *subpass) struct anv_subpass *subpass)
{ {
cmd_buffer->state.subpass = subpass; cmd_buffer->state.subpass = subpass;
cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT; cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
gen7_cmd_buffer_emit_depth_stencil(cmd_buffer); cmd_buffer_emit_depth_stencil(cmd_buffer);
} }
static void static void
@@ -890,7 +903,7 @@ begin_render_pass(struct anv_cmd_buffer *cmd_buffer,
pRenderPassBegin->pClearValues); pRenderPassBegin->pClearValues);
} }
void gen7_CmdBeginRenderPass( void genX(CmdBeginRenderPass)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
const VkRenderPassBeginInfo* pRenderPassBegin, const VkRenderPassBeginInfo* pRenderPassBegin,
VkRenderPassContents contents) VkRenderPassContents contents)
@@ -903,7 +916,7 @@ void gen7_CmdBeginRenderPass(
gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses); gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
} }
void gen7_CmdNextSubpass( void genX(CmdNextSubpass)(
VkCmdBuffer cmdBuffer, VkCmdBuffer cmdBuffer,
VkRenderPassContents contents) VkRenderPassContents contents)
{ {
@@ -914,7 +927,7 @@ void gen7_CmdNextSubpass(
gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1); gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
} }
void gen7_CmdEndRenderPass( void genX(CmdEndRenderPass)(
VkCmdBuffer cmdBuffer) VkCmdBuffer cmdBuffer)
{ {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);

22
src/vulkan/gen7_pipeline.c
View File

@@ -30,6 +30,7 @@
#include "anv_private.h" #include "anv_private.h"
#include "gen7_pack.h" #include "gen7_pack.h"
#include "gen75_pack.h"
static void static void
gen7_emit_vertex_input(struct anv_pipeline *pipeline, gen7_emit_vertex_input(struct anv_pipeline *pipeline,
@@ -341,8 +342,8 @@ scratch_space(const struct brw_stage_prog_data *prog_data)
return ffs(prog_data->total_scratch / 1024); return ffs(prog_data->total_scratch / 1024);
} }
VkResult GENX_FUNC(GEN7, GEN75) VkResult
gen7_graphics_pipeline_create( genX(graphics_pipeline_create)(
VkDevice _device, VkDevice _device,
const VkGraphicsPipelineCreateInfo* pCreateInfo, const VkGraphicsPipelineCreateInfo* pCreateInfo,
const struct anv_graphics_pipeline_create_info *extra, const struct anv_graphics_pipeline_create_info *extra,
@@ -478,9 +479,9 @@ gen7_graphics_pipeline_create(
#endif #endif
if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false);
else else
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS),
.KernelStartPointer = pipeline->vs_vec4, .KernelStartPointer = pipeline->vs_vec4,
.ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX], .ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
.PerThreadScratchSpace = scratch_space(&vue_prog_data->base), .PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
@@ -497,12 +498,12 @@ gen7_graphics_pipeline_create(
const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data; const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) { if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false); anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false);
} else { } else {
urb_offset = 1; urb_offset = 1;
urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset; urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
.KernelStartPointer = pipeline->gs_vec4, .KernelStartPointer = pipeline->gs_vec4,
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY], .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base), .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
@@ -521,7 +522,11 @@ gen7_graphics_pipeline_create(
.DispatchMode = gs_prog_data->base.dispatch_mode, .DispatchMode = gs_prog_data->base.dispatch_mode,
.GSStatisticsEnable = true, .GSStatisticsEnable = true,
.IncludePrimitiveID = gs_prog_data->include_primitive_id, .IncludePrimitiveID = gs_prog_data->include_primitive_id,
# if (ANV_IS_HASWELL)
.ReorderMode = REORDER_TRAILING,
# else
.ReorderEnable = true, .ReorderEnable = true,
# endif
.GSEnable = true); .GSEnable = true);
} }
@@ -539,7 +544,7 @@ gen7_graphics_pipeline_create(
.VertexURBEntryReadOffset = urb_offset, .VertexURBEntryReadOffset = urb_offset,
.PointSpriteTextureCoordinateOrigin = UPPERLEFT); .PointSpriteTextureCoordinateOrigin = UPPERLEFT);
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS, anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS),
.KernelStartPointer0 = pipeline->ps_ksp0, .KernelStartPointer0 = pipeline->ps_ksp0,
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT], .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
.PerThreadScratchSpace = scratch_space(&wm_prog_data->base), .PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
@@ -589,7 +594,8 @@ gen7_graphics_pipeline_create(
return VK_SUCCESS; return VK_SUCCESS;
} }
VkResult gen7_compute_pipeline_create( GENX_FUNC(GEN7, GEN75) VkResult
genX(compute_pipeline_create)(
VkDevice _device, VkDevice _device,
const VkComputePipelineCreateInfo* pCreateInfo, const VkComputePipelineCreateInfo* pCreateInfo,
VkPipeline* pPipeline) VkPipeline* pPipeline)

58
src/vulkan/gen7_state.c
View File

@@ -30,29 +30,37 @@
#include "anv_private.h" #include "anv_private.h"
#include "gen7_pack.h" #include "gen7_pack.h"
#include "gen75_pack.h"
void GENX_FUNC(GEN7, GEN75) void
gen7_fill_buffer_surface_state(void *state, const struct anv_format *format, genX(fill_buffer_surface_state)(void *state, const struct anv_format *format,
uint32_t offset, uint32_t range, uint32_t stride) uint32_t offset, uint32_t range,
uint32_t stride)
{ {
uint32_t num_elements = range / stride; uint32_t num_elements = range / stride;
struct GEN7_RENDER_SURFACE_STATE surface_state = { struct GENX(RENDER_SURFACE_STATE) surface_state = {
.SurfaceType = SURFTYPE_BUFFER, .SurfaceType = SURFTYPE_BUFFER,
.SurfaceFormat = format->surface_format, .SurfaceFormat = format->surface_format,
.SurfaceVerticalAlignment = VALIGN_4, .SurfaceVerticalAlignment = VALIGN_4,
.SurfaceHorizontalAlignment = HALIGN_4, .SurfaceHorizontalAlignment = HALIGN_4,
.TiledSurface = false, .TiledSurface = false,
.RenderCacheReadWriteMode = false, .RenderCacheReadWriteMode = false,
.SurfaceObjectControlState = GEN7_MOCS, .SurfaceObjectControlState = GENX(MOCS),
.Height = (num_elements >> 7) & 0x3fff, .Height = (num_elements >> 7) & 0x3fff,
.Width = num_elements & 0x7f, .Width = num_elements & 0x7f,
.Depth = (num_elements >> 21) & 0x3f, .Depth = (num_elements >> 21) & 0x3f,
.SurfacePitch = stride - 1, .SurfacePitch = stride - 1,
# if (ANV_IS_HASWELL)
.ShaderChannelSelectR = SCS_RED,
.ShaderChannelSelectG = SCS_GREEN,
.ShaderChannelSelectB = SCS_BLUE,
.ShaderChannelSelectA = SCS_ALPHA,
# endif
.SurfaceBaseAddress = { NULL, offset }, .SurfaceBaseAddress = { NULL, offset },
}; };
GEN7_RENDER_SURFACE_STATE_pack(NULL, state, &surface_state); GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
} }
static const uint32_t vk_to_gen_tex_filter[] = { static const uint32_t vk_to_gen_tex_filter[] = {
@@ -86,7 +94,7 @@ static const uint32_t vk_to_gen_compare_op[] = {
}; };
static struct anv_state static struct anv_state
gen7_alloc_surface_state(struct anv_device *device, alloc_surface_state(struct anv_device *device,
struct anv_cmd_buffer *cmd_buffer) struct anv_cmd_buffer *cmd_buffer)
{ {
if (cmd_buffer) { if (cmd_buffer) {
@@ -96,7 +104,7 @@ gen7_alloc_surface_state(struct anv_device *device,
} }
} }
VkResult gen7_CreateSampler( VkResult genX(CreateSampler)(
VkDevice _device, VkDevice _device,
const VkSamplerCreateInfo* pCreateInfo, const VkSamplerCreateInfo* pCreateInfo,
VkSampler* pSampler) VkSampler* pSampler)
@@ -174,8 +182,17 @@ static const uint8_t anv_valign[] = {
[4] = VALIGN_4, [4] = VALIGN_4,
}; };
void static const uint32_t vk_to_gen_swizzle[] = {
gen7_image_view_init(struct anv_image_view *iview, [VK_CHANNEL_SWIZZLE_ZERO] = SCS_ZERO,
[VK_CHANNEL_SWIZZLE_ONE] = SCS_ONE,
[VK_CHANNEL_SWIZZLE_R] = SCS_RED,
[VK_CHANNEL_SWIZZLE_G] = SCS_GREEN,
[VK_CHANNEL_SWIZZLE_B] = SCS_BLUE,
[VK_CHANNEL_SWIZZLE_A] = SCS_ALPHA
};
GENX_FUNC(GEN7, GEN75) void
genX(image_view_init)(struct anv_image_view *iview,
struct anv_device *device, struct anv_device *device,
const VkImageViewCreateInfo* pCreateInfo, const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer) struct anv_cmd_buffer *cmd_buffer)
@@ -211,7 +228,7 @@ gen7_image_view_init(struct anv_image_view *iview,
depth = image->extent.depth; depth = image->extent.depth;
} }
struct GEN7_RENDER_SURFACE_STATE surface_state = { struct GENX(RENDER_SURFACE_STATE) surface_state = {
.SurfaceType = image->surface_type, .SurfaceType = image->surface_type,
.SurfaceArray = image->array_size > 1, .SurfaceArray = image->array_size > 1,
.SurfaceFormat = format->surface_format, .SurfaceFormat = format->surface_format,
@@ -239,23 +256,29 @@ gen7_image_view_init(struct anv_image_view *iview,
.XOffset = 0, .XOffset = 0,
.YOffset = 0, .YOffset = 0,
.SurfaceObjectControlState = GEN7_MOCS, .SurfaceObjectControlState = GENX(MOCS),
.MIPCountLOD = 0, /* TEMPLATE */ .MIPCountLOD = 0, /* TEMPLATE */
.SurfaceMinLOD = 0, /* TEMPLATE */ .SurfaceMinLOD = 0, /* TEMPLATE */
.MCSEnable = false, .MCSEnable = false,
# if (ANV_IS_HASWELL)
.ShaderChannelSelectR = vk_to_gen_swizzle[pCreateInfo->channels.r],
.ShaderChannelSelectG = vk_to_gen_swizzle[pCreateInfo->channels.g],
.ShaderChannelSelectB = vk_to_gen_swizzle[pCreateInfo->channels.b],
.ShaderChannelSelectA = vk_to_gen_swizzle[pCreateInfo->channels.a],
# else /* XXX: Seriously? */
.RedClearColor = 0, .RedClearColor = 0,
.GreenClearColor = 0, .GreenClearColor = 0,
.BlueClearColor = 0, .BlueClearColor = 0,
.AlphaClearColor = 0, .AlphaClearColor = 0,
# endif
.ResourceMinLOD = 0.0, .ResourceMinLOD = 0.0,
.SurfaceBaseAddress = { NULL, iview->offset }, .SurfaceBaseAddress = { NULL, iview->offset },
}; };
if (image->needs_nonrt_surface_state) { if (image->needs_nonrt_surface_state) {
iview->nonrt_surface_state = iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer);
gen7_alloc_surface_state(device, cmd_buffer);
surface_state.RenderCacheReadWriteMode = false; surface_state.RenderCacheReadWriteMode = false;
@@ -266,13 +289,12 @@ gen7_image_view_init(struct anv_image_view *iview,
surface_state.SurfaceMinLOD = range->baseMipLevel; surface_state.SurfaceMinLOD = range->baseMipLevel;
surface_state.MIPCountLOD = range->mipLevels - 1; surface_state.MIPCountLOD = range->mipLevels - 1;
GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->nonrt_surface_state.map, GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map,
&surface_state); &surface_state);
} }
if (image->needs_color_rt_surface_state) { if (image->needs_color_rt_surface_state) {
iview->color_rt_surface_state = iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer);
gen7_alloc_surface_state(device, cmd_buffer);
surface_state.RenderCacheReadWriteMode = 0; /* Write only */ surface_state.RenderCacheReadWriteMode = 0; /* Write only */
@@ -285,7 +307,7 @@ gen7_image_view_init(struct anv_image_view *iview,
surface_state.MIPCountLOD = range->baseMipLevel; surface_state.MIPCountLOD = range->baseMipLevel;
surface_state.SurfaceMinLOD = 0; surface_state.SurfaceMinLOD = 0;
GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->color_rt_surface_state.map, GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map,
&surface_state); &surface_state);
} }
} }