panfrost: XML-ify the bifrost tiler descriptors
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6797>
This commit is contained in:
Boris Brezillon
committed by
Alyssa Rosenzweig
Alyssa Rosenzweig
parent
95eb7d9a34
commit
efce73d99d
@@ -1811,7 +1811,7 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch,
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bifrost_tiler.prefix = *tiler_prefix;
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bifrost_tiler.primitive_size = *primitive_size;
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bifrost_tiler.tiler_meta = panfrost_batch_get_tiler_meta(batch, ~0);
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bifrost_tiler.tiler_meta = panfrost_batch_get_bifrost_tiler(batch, ~0);
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memcpy(&bifrost_tiler.postfix, tiler_draw, MALI_DRAW_LENGTH);
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tp = &bifrost_tiler;
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tp_size = sizeof(bifrost_tiler);
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@@ -678,7 +678,7 @@ panfrost_batch_get_shared_memory(struct panfrost_batch *batch,
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}
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mali_ptr
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panfrost_batch_get_tiler_meta(struct panfrost_batch *batch, unsigned vertex_count)
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panfrost_batch_get_bifrost_tiler(struct panfrost_batch *batch, unsigned vertex_count)
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{
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if (!vertex_count)
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return 0;
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@@ -687,25 +687,27 @@ panfrost_batch_get_tiler_meta(struct panfrost_batch *batch, unsigned vertex_coun
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return batch->tiler_meta;
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struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
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struct panfrost_transfer t =
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panfrost_pool_alloc_aligned(&batch->pool, MALI_BIFROST_TILER_HEAP_LENGTH, 64);
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struct bifrost_tiler_heap_meta tiler_heap_meta = {
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.heap_size = dev->tiler_heap->size,
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.tiler_heap_start = dev->tiler_heap->gpu,
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.tiler_heap_free = dev->tiler_heap->gpu,
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.tiler_heap_end = dev->tiler_heap->gpu + dev->tiler_heap->size,
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.unk1 = 0x1,
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.unk7e007e = 0x7e007e,
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};
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pan_pack(t.cpu, BIFROST_TILER_HEAP, heap) {
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heap.size = dev->tiler_heap->size;
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heap.base = dev->tiler_heap->gpu;
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heap.bottom = dev->tiler_heap->gpu;
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heap.top = dev->tiler_heap->gpu + dev->tiler_heap->size;
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}
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struct bifrost_tiler_meta tiler_meta = {
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.hierarchy_mask = 0x28,
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.flags = 0x0,
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.width = MALI_POSITIVE(batch->key.width),
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.height = MALI_POSITIVE(batch->key.height),
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.tiler_heap_meta = panfrost_pool_upload_aligned(&batch->pool, &tiler_heap_meta, sizeof(tiler_heap_meta), 64)
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};
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mali_ptr heap = t.gpu;
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batch->tiler_meta = panfrost_pool_upload_aligned(&batch->pool, &tiler_meta, sizeof(tiler_meta), 64);
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t = panfrost_pool_alloc_aligned(&batch->pool, MALI_BIFROST_TILER_LENGTH, 64);
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pan_pack(t.cpu, BIFROST_TILER, tiler) {
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tiler.hierarchy_mask = 0x28;
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tiler.fb_width = batch->key.width;
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tiler.fb_height = batch->key.height;
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tiler.heap = heap;
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}
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batch->tiler_meta = t.gpu;
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return batch->tiler_meta;
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}
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@@ -205,7 +205,7 @@ bool
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panfrost_batch_is_scanout(struct panfrost_batch *batch);
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mali_ptr
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panfrost_batch_get_tiler_meta(struct panfrost_batch *batch, unsigned vertex_count);
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panfrost_batch_get_bifrost_tiler(struct panfrost_batch *batch, unsigned vertex_count);
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mali_ptr
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panfrost_batch_reserve_framebuffer(struct panfrost_batch *batch);
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@@ -496,7 +496,7 @@ panfrost_emit_mfbd(struct panfrost_batch *batch, unsigned vertex_count)
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if (dev->quirks & IS_BIFROST) {
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mfbd.msaa.sample_locations = panfrost_emit_sample_locations(batch);
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mfbd.tiler_meta = panfrost_batch_get_tiler_meta(batch, vertex_count);
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mfbd.tiler_meta = panfrost_batch_get_bifrost_tiler(batch, vertex_count);
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} else {
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struct mali_local_storage_packed lsp;
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@@ -422,33 +422,6 @@ union midgard_primitive_size {
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u64 pointer;
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};
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struct bifrost_tiler_heap_meta {
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u32 zero;
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u32 heap_size;
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/* note: these are just guesses! */
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mali_ptr tiler_heap_start;
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mali_ptr tiler_heap_free;
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mali_ptr tiler_heap_end;
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/* hierarchy weights? but they're still 0 after the job has run... */
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u32 zeros[10];
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u32 unk1;
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u32 unk7e007e;
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} __attribute__((packed));
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struct bifrost_tiler_meta {
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u32 tiler_heap_next_start; /* To be written by the GPU */
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u32 used_hierarchy_mask; /* To be written by the GPU */
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u16 hierarchy_mask; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
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u16 flags;
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u16 width;
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u16 height;
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u64 zero0;
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mali_ptr tiler_heap_meta;
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/* TODO what is this used for? */
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u64 zeros[20];
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} __attribute__((packed));
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struct midgard_payload_vertex_tiler {
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struct mali_vertex_tiler_prefix prefix;
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struct mali_draw_packed postfix;
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@@ -1577,99 +1577,31 @@ pandecode_vertex_tiler_postfix_pre(
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}
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static void
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pandecode_tiler_heap_meta(mali_ptr gpu_va, int job_no)
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pandecode_bifrost_tiler_heap(mali_ptr gpu_va, int job_no)
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{
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struct pandecode_mapped_memory *mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
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const struct bifrost_tiler_heap_meta *PANDECODE_PTR_VAR(h, mem, gpu_va);
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pandecode_log("struct bifrost_tiler_heap_meta tiler_heap_meta_%"PRIx64"_%d = {\n", gpu_va, job_no);
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pandecode_indent++;
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if (h->zero) {
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pandecode_msg("XXX: tiler heap zero tripped\n");
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pandecode_prop("zero = 0x%x", h->zero);
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}
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pandecode_prop("heap_size = 0x%x", h->heap_size);
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MEMORY_PROP(h, tiler_heap_start);
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MEMORY_PROP(h, tiler_heap_free);
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/* this might point to the beginning of another buffer, when it's
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* really the end of the tiler heap buffer, so we have to be careful
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* here. but for zero length, we need the same pointer.
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*/
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if (h->tiler_heap_end == h->tiler_heap_start) {
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MEMORY_PROP(h, tiler_heap_start);
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} else {
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char *a = pointer_as_memory_reference(h->tiler_heap_end - 1);
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pandecode_prop("tiler_heap_end = %s + 1", a);
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free(a);
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}
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for (int i = 0; i < 10; i++) {
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if (h->zeros[i] != 0) {
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pandecode_msg("XXX: tiler heap zero %d tripped, value %x\n",
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i, h->zeros[i]);
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}
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}
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if (h->unk1 != 0x1) {
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pandecode_msg("XXX: tiler heap unk1 tripped\n");
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pandecode_prop("unk1 = 0x%x", h->unk1);
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}
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if (h->unk7e007e != 0x7e007e) {
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pandecode_msg("XXX: tiler heap unk7e007e tripped\n");
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pandecode_prop("unk7e007e = 0x%x", h->unk7e007e);
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}
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pandecode_indent--;
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pandecode_log("};\n");
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pan_unpack(PANDECODE_PTR(mem, gpu_va, void), BIFROST_TILER_HEAP, h);
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DUMP_UNPACKED(BIFROST_TILER_HEAP, h, "Bifrost Tiler Heap:\n");
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}
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static void
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pandecode_tiler_meta(mali_ptr gpu_va, int job_no)
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pandecode_bifrost_tiler(mali_ptr gpu_va, int job_no)
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{
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struct pandecode_mapped_memory *mem = pandecode_find_mapped_gpu_mem_containing(gpu_va);
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const struct bifrost_tiler_meta *PANDECODE_PTR_VAR(t, mem, gpu_va);
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pan_unpack(PANDECODE_PTR(mem, gpu_va, void), BIFROST_TILER, t);
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pandecode_tiler_heap_meta(t->tiler_heap_meta, job_no);
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pandecode_bifrost_tiler_heap(t.heap, job_no);
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pandecode_log("struct bifrost_tiler_meta tiler_meta_%"PRIx64"_%d = {\n", gpu_va, job_no);
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DUMP_UNPACKED(BIFROST_TILER, t, "Bifrost Tiler:\n");
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pandecode_indent++;
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pandecode_prop("tiler_heap_next_start = 0x%" PRIx32, t->tiler_heap_next_start);
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pandecode_prop("used_hierarchy_mask = 0x%" PRIx32, t->used_hierarchy_mask);
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if (t->hierarchy_mask != 0xa &&
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t->hierarchy_mask != 0x14 &&
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t->hierarchy_mask != 0x28 &&
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t->hierarchy_mask != 0x50 &&
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t->hierarchy_mask != 0xa0)
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if (t.hierarchy_mask != 0xa &&
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t.hierarchy_mask != 0x14 &&
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t.hierarchy_mask != 0x28 &&
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t.hierarchy_mask != 0x50 &&
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t.hierarchy_mask != 0xa0)
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pandecode_prop("XXX: Unexpected hierarchy_mask (not 0xa, 0x14, 0x28, 0x50 or 0xa0)!");
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pandecode_prop("hierarchy_mask = 0x%" PRIx16, t->hierarchy_mask);
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pandecode_prop("flags = 0x%" PRIx16, t->flags);
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pandecode_prop("width = MALI_POSITIVE(%d)", t->width + 1);
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pandecode_prop("height = MALI_POSITIVE(%d)", t->height + 1);
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if (t->zero0) {
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pandecode_msg("XXX: tiler meta zero tripped\n");
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pandecode_prop("zero0 = 0x%" PRIx64, t->zero0);
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}
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for (int i = 0; i < 12; i++) {
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if (t->zeros[i] != 0) {
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pandecode_msg("XXX: tiler heap zero %d tripped, value %" PRIx64 "\n",
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i, t->zeros[i]);
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}
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}
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pandecode_indent--;
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pandecode_log("};\n");
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}
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static void
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@@ -1720,7 +1652,7 @@ pandecode_tiler_job_bfr(const struct mali_job_descriptor_header *h,
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memcpy(&draw_packed, &t->postfix, sizeof(draw_packed));
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pan_unpack(&draw_packed, DRAW, draw);
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pandecode_vertex_tiler_postfix_pre(&draw, job_no, h->job_type, "", true, gpu_id);
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pandecode_tiler_meta(t->tiler_meta, job_no);
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pandecode_bifrost_tiler(t->tiler_meta, job_no);
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pandecode_vertex_tiler_prefix(&t->prefix, job_no, false);
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@@ -751,4 +751,34 @@
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<section name="Tiler Weights" offset="256" type="Midgard Tiler Weights"/>
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<section name="Padding 2" offset="288" type="Single-Target Framebuffer Padding 2"/>
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</aggregate>
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<enum name="Sample Pattern">
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<value name="Single-sampled" value="0"/>
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<value name="Ordered 4x Grid" value="1"/>
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<value name="Rotated 4x Grid" value="2"/>
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<value name="D3D 8x Grid" value="3"/>
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<value name="D3D 16x Grid" value="4"/>
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</enum>
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<struct name="Bifrost Tiler Heap">
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<field name="Size" size="32" start="1:0" type="uint" modifier="align(4096)"/>
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<field name="Base" size="64" start="2:0" type="address"/>
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<field name="Bottom" size="64" start="4:0" type="address"/>
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<field name="Top" size="64" start="6:0" type="address"/>
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</struct>
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<struct name="Bifrost Tiler Weights" size="1">
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<field name="Value" size="16" start="0:16" type="uint"/>
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</struct>
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<struct name="Bifrost Tiler">
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<field name="Polygon List" size="64" start="0:0" type="address"/>
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<field name="Hierarchy Mask" size="13" start="2:0" type="uint"/>
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<field name="Sample Pattern" size="3" start="2:13" type="Sample Pattern"/>
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<field name="Update Cost Table" size="1" start="2:16" type="bool"/>
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<field name="FB Width" size="16" start="3:0" type="uint" modifier="minus(1)"/>
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<field name="FB Height" size="16" start="3:16" type="uint" modifier="minus(1)"/>
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<field name="Heap" size="64" start="6:0" type="address"/>
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<field name="Weights" size="32" start="8:0" type="Bifrost Tiler Weights" elements="8"/>
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</struct>
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</panxml>
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