OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pvr: Use driver vertex input data in the compiler

Browse Source 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21588>
This commit is contained in:
Simon Perretta
2023-02-27 13:57:19 +00:00
committed by Marge Bot
parent 361f58f0ee
commit efc629389a
3 changed files with 57 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
src/imagination/rogue/rogue_build_data.c
View File

@@ -186,27 +186,6 @@ static void collect_io_data_fs(struct rogue_common_build_data *common_data,
/* TODO: Process outputs. */
}
/**
* \brief Allocates the vertex shader input registers.
*
* \param[in] inputs The vertex shader input data.
* \return The total number of vertex input registers required.
*/
static unsigned alloc_vs_inputs(struct rogue_vertex_inputs *inputs)
{
unsigned vs_inputs = 0;
for (unsigned u = 0; u < inputs->num_input_vars; ++u) {
/* Ensure there aren't any gaps. */
assert(inputs->base[u] == ~0);
inputs->base[u] = vs_inputs;
vs_inputs += inputs->components[u];
}
return vs_inputs;
}
/**
* \brief Allocates the vertex shader outputs.
*
@@ -302,28 +281,6 @@ static void collect_io_data_vs(struct rogue_common_build_data *common_data,
ASSERTED unsigned num_outputs =
nir_count_variables_with_modes(nir, nir_var_shader_out);
/* Process inputs. */
nir_foreach_shader_in_variable (var, nir) {
unsigned components = glsl_get_components(var->type);
unsigned i = var->data.location - VERT_ATTRIB_GENERIC0;
/* Check that inputs are F32. */
/* TODO: Support other types. */
assert(glsl_get_base_type(var->type) == GLSL_TYPE_FLOAT);
assert(glsl_type_is_32bit(var->type));
/* Check input location. */
assert(var->data.location >= VERT_ATTRIB_GENERIC0 &&
var->data.location <= VERT_ATTRIB_GENERIC15);
reserve_vs_input(&vs_data->inputs, i, components);
}
vs_data->num_vertex_input_regs = alloc_vs_inputs(&vs_data->inputs);
assert(vs_data->num_vertex_input_regs);
assert(vs_data->num_vertex_input_regs <
rogue_reg_infos[ROGUE_REG_CLASS_VTXIN].num);
/* Process outputs. */
/* We should always have at least a position variable. */

47
src/imagination/rogue/rogue_compile.c
View File

@@ -180,16 +180,57 @@ static void trans_nir_intrinsic_load_input_fs(rogue_builder *b,
static void trans_nir_intrinsic_load_input_vs(rogue_builder *b,
nir_intrinsic_instr *intr)
{
struct pvr_pipeline_layout *pipeline_layout =
b->shader->ctx->pipeline_layout;
ASSERTED unsigned load_size = nir_dest_num_components(intr->dest);
assert(load_size == 1); /* TODO: We can support larger load sizes. */
rogue_reg *dst = rogue_ssa_reg(b->shader, intr->dest.ssa.index);
struct nir_io_semantics io_semantics = nir_intrinsic_io_semantics(intr);
unsigned input = io_semantics.location - VERT_ATTRIB_GENERIC0;
unsigned component = nir_intrinsic_component(intr);
/* TODO: Get these properly with the intrinsic index (ssa argument) */
unsigned vtxin_index =
((io_semantics.location - VERT_ATTRIB_GENERIC0) * 3) + component;
unsigned vtxin_index = ~0U;
if (pipeline_layout) {
rogue_vertex_inputs *vs_inputs = &b->shader->ctx->stage_data.vs.inputs;
assert(input < vs_inputs->num_input_vars);
assert(component < vs_inputs->components[input]);
vtxin_index = vs_inputs->base[input] + component;
} else {
/* Dummy defaults for offline compiler. */
/* TODO: Load these from an offline description
* if using the offline compiler.
*/
nir_shader *nir = b->shader->ctx->nir[MESA_SHADER_VERTEX];
vtxin_index = 0;
/* Process inputs. */
nir_foreach_shader_in_variable (var, nir) {
unsigned input_components = glsl_get_components(var->type);
unsigned bit_size =
glsl_base_type_bit_size(glsl_get_base_type(var->type));
assert(bit_size >= 32); /* TODO: Support smaller bit sizes. */
unsigned reg_count = bit_size / 32;
/* Check input location. */
assert(var->data.location >= VERT_ATTRIB_GENERIC0 &&
var->data.location <= VERT_ATTRIB_GENERIC15);
if (var->data.location == io_semantics.location) {
assert(component < input_components);
vtxin_index += reg_count * component;
break;
}
vtxin_index += reg_count * input_components;
}
}
assert(vtxin_index != ~0U);
rogue_reg *src = rogue_vtxin_reg(b->shader, vtxin_index);
rogue_instr *instr =

25
src/imagination/vulkan/pvr_pipeline.c
View File

@@ -1848,17 +1848,23 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
/* Vars needed for the new path. */
struct pvr_pds_vertex_dma vtx_dma_descriptions[PVR_MAX_VERTEX_ATTRIB_DMAS];
uint32_t vtx_dma_count = 0;
/* TODO: This should be used by the compiler for compiler the vertex shader.
*/
rogue_vertex_inputs vertex_input_layout;
unsigned vertex_input_reg_count = 0;
rogue_vertex_inputs *vertex_input_layout;
unsigned *vertex_input_reg_count;
uint32_t sh_count[PVR_STAGE_ALLOCATION_COUNT] = { 0 };
/* Setup shared build context. */
ctx = rogue_build_context_create(compiler, layout);
if (!ctx)
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
vertex_input_layout = &ctx->stage_data.vs.inputs;
vertex_input_reg_count = &ctx->stage_data.vs.num_vertex_input_regs;
if (!old_path) {
pvr_graphics_pipeline_alloc_vertex_inputs(vertex_input_state,
&vertex_input_layout,
&vertex_input_reg_count,
vertex_input_layout,
vertex_input_reg_count,
&vtx_dma_descriptions,
&vtx_dma_count);
@@ -1873,11 +1879,6 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
&layout->sh_reg_layout_per_stage[pvr_stage]);
}
/* Setup shared build context. */
ctx = rogue_build_context_create(compiler, layout);
if (!ctx)
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
/* NIR middle-end translation. */
for (gl_shader_stage stage = MESA_SHADER_FRAGMENT; stage > MESA_SHADER_NONE;
stage--) {
@@ -1974,7 +1975,7 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
} else {
pvr_vertex_state_init(gfx_pipeline,
&ctx->common_data[MESA_SHADER_VERTEX],
vertex_input_reg_count,
*vertex_input_reg_count,
&ctx->stage_data.vs);
if (!old_path) {