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/*
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* Copyright © 2014 Intel Corporation
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* Copyright © 2015 Red Hat
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Jason Ekstrand (jason@jlekstrand.net)
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* Rob Clark (robclark@freedesktop.org)
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*
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*/
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#include "ir3_nir.h"
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#include "glsl/nir/nir_builder.h"
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/* Based on nir_opt_peephole_select, and hacked up to more aggressively
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* flatten anything that can be flattened
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*
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* This *might* be something that other drivers could use. On the other
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* hand, I think most other hw has predicated instructions or similar
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* to select which side of if/else writes back result (and therefore
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* not having to assign unique registers to both sides of the if/else.
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* (And hopefully those drivers don't also have crazy scheduling reqs
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* and can more easily do this in their backend.)
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*
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* TODO eventually when we have proper flow control in the backend:
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*
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* + Probably weight differently normal ALUs vs SFUs (cos/rcp/exp)
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* since executing extra SFUs for the branch-not-taken path will
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* generally be much more expensive.
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*
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* Possibly what constitutes an ALU vs SFU differs between hw
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* backends.. but that seems doubtful.
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*
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* + Account for texture fetch and memory accesses (incl UBOs)
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* since these will be more expensive..
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*
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* + When if-condition is const (or uniform) or we have some way
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* to know that all threads in the warp take the same branch
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* then we should prefer to not flatten the if/else..
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*/
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struct lower_state {
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nir_builder b;
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void *mem_ctx;
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bool progress;
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};
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static bool
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valid_dest(nir_block *block, nir_dest *dest)
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{
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/* It must be SSA */
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if (!dest->is_ssa)
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return false;
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/* We only lower blocks that do not contain other blocks
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* (so this is run iteratively in a loop). Therefore if
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* we get this far, it should not have any if_uses:
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*/
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assert(dest->ssa.if_uses->entries == 0);
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/* The only uses of this definition must be phi's in the
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* successor or in the current block
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*/
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struct set_entry *entry;
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set_foreach(dest->ssa.uses, entry) {
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const nir_instr *dest_instr = entry->key;
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if (dest_instr->block == block)
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continue;
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if ((dest_instr->type == nir_instr_type_phi) &&
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(dest_instr->block == block->successors[0]))
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continue;
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return false;
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}
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return true;
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}
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static bool
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block_check_for_allowed_instrs(nir_block *block)
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{
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nir_foreach_instr(block, instr) {
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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const nir_intrinsic_info *info =
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&nir_intrinsic_infos[intr->intrinsic];
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switch (intr->intrinsic) {
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case nir_intrinsic_discard_if:
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/* to simplify things, we want discard_if src in ssa: */
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if (!intr->src[0].is_ssa)
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return false;
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/* fallthrough */
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case nir_intrinsic_discard:
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/* discard/discard_if can be reordered, but only
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* with some special care
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*/
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break;
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case nir_intrinsic_store_output:
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/* TODO technically, if both if and else store
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* the same output, we can hoist that out to
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* the end of the block w/ a phi..
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* In practice, the tgsi shaders we already get
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* do this for us, so I think we don't need to
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*/
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default:
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if (!(info->flags & NIR_INTRINSIC_CAN_REORDER))
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return false;
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}
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break;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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if (!valid_dest(block, &tex->dest))
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return false;
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break;
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}
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case nir_instr_type_phi: {
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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if (!valid_dest(block, &phi->dest))
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return false;
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break;
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}
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case nir_instr_type_alu: {
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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if (!valid_dest(block, &alu->dest.dest))
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return false;
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break;
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}
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case nir_instr_type_load_const:
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case nir_instr_type_ssa_undef:
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break; /* always ssa dest */
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default:
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return false;
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}
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}
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return true;
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}
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/* flatten an then or else block: */
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static void
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flatten_block(nir_builder *bld, nir_block *if_block, nir_block *prev_block,
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nir_ssa_def *condition, bool invert)
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{
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nir_foreach_instr_safe(if_block, instr) {
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if (instr->type == nir_instr_type_intrinsic) {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if ((intr->intrinsic == nir_intrinsic_discard) ||
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(intr->intrinsic == nir_intrinsic_discard_if)) {
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nir_ssa_def *discard_cond;
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nir_builder_insert_after_instr(bld,
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nir_block_last_instr(prev_block));
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if (invert) {
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condition = nir_inot(bld, condition);
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invert = false;
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}
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if (intr->intrinsic == nir_intrinsic_discard) {
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discard_cond = condition;
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} else {
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assert(intr->src[0].is_ssa);
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/* discard_if gets re-written w/ src and'd: */
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discard_cond = nir_iand(bld, condition, intr->src[0].ssa);
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}
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nir_intrinsic_instr *discard_if =
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nir_intrinsic_instr_create(bld->shader,
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nir_intrinsic_discard_if);
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discard_if->src[0] = nir_src_for_ssa(discard_cond);
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nir_instr_insert_after(nir_block_last_instr(prev_block),
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&discard_if->instr);
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nir_instr_remove(instr);
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instr = NULL;
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}
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}
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/* if not an handled specially, just move to prev block: */
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if (instr) {
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/* NOTE: exec_node_remove() is safe here (vs nir_instr_remove()
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* since we are re-adding the instructin back in to the prev
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* block (so no dangling SSA uses)
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*/
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exec_node_remove(&instr->node);
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instr->block = prev_block;
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exec_list_push_tail(&prev_block->instr_list, &instr->node);
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}
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}
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}
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static bool
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lower_if_else_block(nir_block *block, void *void_state)
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{
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struct lower_state *state = void_state;
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/* If the block is empty, then it certainly doesn't have any phi nodes,
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* so we can skip it. This also ensures that we do an early skip on the
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* end block of the function which isn't actually attached to the CFG.
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*/
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if (exec_list_is_empty(&block->instr_list))
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return true;
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if (nir_cf_node_is_first(&block->cf_node))
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return true;
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nir_cf_node *prev_node = nir_cf_node_prev(&block->cf_node);
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if (prev_node->type != nir_cf_node_if)
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return true;
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nir_if *if_stmt = nir_cf_node_as_if(prev_node);
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nir_cf_node *then_node = nir_if_first_then_node(if_stmt);
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nir_cf_node *else_node = nir_if_first_else_node(if_stmt);
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/* We can only have one block in each side ... */
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if (nir_if_last_then_node(if_stmt) != then_node ||
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nir_if_last_else_node(if_stmt) != else_node)
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return true;
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nir_block *then_block = nir_cf_node_as_block(then_node);
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nir_block *else_block = nir_cf_node_as_block(else_node);
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/* ... and those blocks must only contain "allowed" instructions. */
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if (!block_check_for_allowed_instrs(then_block) ||
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!block_check_for_allowed_instrs(else_block))
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return true;
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/* condition should be ssa too, which simplifies flatten_block: */
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if (!if_stmt->condition.is_ssa)
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return true;
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/* At this point, we know that the previous CFG node is an if-then
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* statement containing only moves to phi nodes in this block. We can
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* just remove that entire CF node and replace all of the phi nodes with
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* selects.
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*/
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nir_block *prev_block = nir_cf_node_as_block(nir_cf_node_prev(prev_node));
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assert(prev_block->cf_node.type == nir_cf_node_block);
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/* First, we move the remaining instructions from the blocks to the
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* block before. There are a few things that need handling specially
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* like discard/discard_if.
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*/
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flatten_block(&state->b, then_block, prev_block,
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if_stmt->condition.ssa, false);
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flatten_block(&state->b, else_block, prev_block,
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if_stmt->condition.ssa, true);
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nir_foreach_instr_safe(block, instr) {
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if (instr->type != nir_instr_type_phi)
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break;
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nir_phi_instr *phi = nir_instr_as_phi(instr);
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nir_alu_instr *sel = nir_alu_instr_create(state->mem_ctx, nir_op_bcsel);
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nir_src_copy(&sel->src[0].src, &if_stmt->condition, state->mem_ctx);
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/* Splat the condition to all channels */
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memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle);
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assert(exec_list_length(&phi->srcs) == 2);
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nir_foreach_phi_src(phi, src) {
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assert(src->pred == then_block || src->pred == else_block);
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assert(src->src.is_ssa);
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unsigned idx = src->pred == then_block ? 1 : 2;
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nir_src_copy(&sel->src[idx].src, &src->src, state->mem_ctx);
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}
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nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
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phi->dest.ssa.num_components, phi->dest.ssa.name);
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sel->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
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nir_ssa_def_rewrite_uses(&phi->dest.ssa,
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nir_src_for_ssa(&sel->dest.dest.ssa),
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state->mem_ctx);
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nir_instr_insert_before(&phi->instr, &sel->instr);
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nir_instr_remove(&phi->instr);
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}
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nir_cf_node_remove(&if_stmt->cf_node);
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state->progress = true;
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return true;
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}
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static bool
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lower_if_else_impl(nir_function_impl *impl)
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{
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struct lower_state state;
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state.mem_ctx = ralloc_parent(impl);
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|
|
|
|
state.progress = false;
|
|
|
|
|
nir_builder_init(&state.b, impl);
|
|
|
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|
|
|
|
|
|
nir_foreach_block(impl, lower_if_else_block, &state);
|
|
|
|
|
|
|
|
|
|
if (state.progress)
|
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_none);
|
|
|
|
|
|
|
|
|
|
return state.progress;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
ir3_nir_lower_if_else(nir_shader *shader)
|
|
|
|
|
{
|
|
|
|
|
bool progress = false;
|
|
|
|
|
|
|
|
|
|
nir_foreach_overload(shader, overload) {
|
|
|
|
|
if (overload->impl)
|
|
|
|
|
progress |= lower_if_else_impl(overload->impl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return progress;
|
|
|
|
|
}
|
Rob Clark