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intel/compiler: Look at 2 register worth of data instead of 4

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Sampler always writes 4/8 register worth of data but for ld_mcs only
valid data is in first two register. So with 16-bit payload, we need to
split 2-32bit registers into 4-16-bit payload.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22802>
This commit is contained in:
Sagar Ghuge
2023-05-01 19:54:07 -07:00
committed by Marge Bot
parent 8b93fa149b
commit efa6594536
1 changed files with 23 additions and 5 deletions
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28
src/intel/compiler/brw_lower_logical_sends.cpp
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@@ -1021,14 +1021,32 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
*
* ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r
*/
if (devinfo->verx10 >= 125 && op == SHADER_OPCODE_TXF_CMS_W)
num_mcs_components = 4;
else if (op == SHADER_OPCODE_TXF_CMS_W)
if (op == SHADER_OPCODE_TXF_CMS_W)
num_mcs_components = 2;
for (unsigned i = 0; i < num_mcs_components; ++i) {
bld.MOV(retype(sources[length++], payload_unsigned_type),
mcs.file == IMM ? mcs : offset(mcs, bld, i));
/* Sampler always writes 4/8 register worth of data but for ld_mcs
* only valid data is in first two register. So with 16-bit
* payload, we need to split 2-32bit register into 4-16-bit
* payload.
*
* From the Gfx12HP BSpec: Render Engine - 3D and GPGPU Programs -
* Shared Functions - 3D Sampler - Messages - Message Format:
*
* ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r
*/
if (devinfo->verx10 >= 125 && op == SHADER_OPCODE_TXF_CMS_W) {
fs_reg tmp = offset(mcs, bld, i);
bld.MOV(retype(sources[length++], payload_unsigned_type),
mcs.file == IMM ? mcs :
subscript(tmp, payload_unsigned_type, 0));
bld.MOV(retype(sources[length++], payload_unsigned_type),
mcs.file == IMM ? mcs :
subscript(tmp, payload_unsigned_type, 1));
} else {
bld.MOV(retype(sources[length++], payload_unsigned_type),
mcs.file == IMM ? mcs : offset(mcs, bld, i));
}
}
}