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anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT

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Gfx12+ PIPE_CONTROL bit for flushing HDC cache and memory
transactions to L3 cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
This commit is contained in:
Felix DeGrood
2021-03-17 19:46:41 -07:00
committed by Marge Bot
parent 82952deb8b
commit ef70388a3a
3 changed files with 9 additions and 0 deletions
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6
src/intel/vulkan/anv_private.h
View File

@@ -2411,6 +2411,12 @@ enum anv_pipe_bits {
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT = (1 << 11),
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT = (1 << 12),
ANV_PIPE_DEPTH_STALL_BIT = (1 << 13),
/* ANV_PIPE_HDC_PIPELINE_FLUSH_BIT is a precise way to ensure prior data
* cache work has completed. Available on Gfx12+. For earlier Gfx we
* must reinterpret this flush as ANV_PIPE_DATA_CACHE_FLUSH_BIT.
*/
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT = (1 << 14),
ANV_PIPE_CS_STALL_BIT = (1 << 20),
ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),

2
src/intel/vulkan/anv_util.c
View File

@@ -121,6 +121,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits)
fputs("+depth_flush ", stderr);
if (bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT)
fputs("+dc_flush ", stderr);
if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
fputs("+hdc_flush ", stderr);
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
fputs("+rt_flush ", stderr);
if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)

1
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -57,6 +57,7 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
#if GFX_VER >= 12
bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
#endif
bits |= (pc->RenderTargetCacheFlushEnable) ? ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
bits |= (pc->StateCacheInvalidationEnable) ? ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;