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anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT

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Gfx12+ PIPE_CONTROL bit for flushing HDC cache and memory
transactions to L3 cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
This commit is contained in:
Felix DeGrood
2021-03-17 19:46:41 -07:00
committed by Marge Bot
parent 82952deb8b
commit ef70388a3a
3 changed files with 9 additions and 0 deletions
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2
src/intel/vulkan/anv_util.c
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@@ -121,6 +121,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits)
fputs("+depth_flush ", stderr);
if (bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT)
fputs("+dc_flush ", stderr);
if (bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT)
fputs("+hdc_flush ", stderr);
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
fputs("+rt_flush ", stderr);
if (bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT)