radv: stop duplicating radv_vs_output_info
Only the last vertex stage needs to access this. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18210>
This commit is contained in:

committed by
Marge Bot

parent
45a0276cd1
commit
ee5b9bcc57
@@ -10910,10 +10910,7 @@ export_vs_varying(isel_context* ctx, int slot, bool is_pos, int* next_pos)
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assert(ctx->stage.hw == HWStage::VS || ctx->stage.hw == HWStage::NGG);
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assert(ctx->stage.hw == HWStage::VS || ctx->stage.hw == HWStage::NGG);
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const uint8_t *vs_output_param_offset =
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const uint8_t *vs_output_param_offset =
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ctx->stage.has(SWStage::GS) ? ctx->program->info.vs.outinfo.vs_output_param_offset :
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ctx->program->info.outinfo.vs_output_param_offset;
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ctx->stage.has(SWStage::TES) ? ctx->program->info.tes.outinfo.vs_output_param_offset :
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ctx->stage.has(SWStage::MS) ? ctx->program->info.ms.outinfo.vs_output_param_offset :
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ctx->program->info.vs.outinfo.vs_output_param_offset;
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assert(vs_output_param_offset);
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assert(vs_output_param_offset);
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@@ -10994,11 +10991,7 @@ static void
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create_vs_exports(isel_context* ctx)
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create_vs_exports(isel_context* ctx)
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{
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{
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assert(ctx->stage.hw == HWStage::VS || ctx->stage.hw == HWStage::NGG);
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assert(ctx->stage.hw == HWStage::VS || ctx->stage.hw == HWStage::NGG);
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const aco_vp_output_info* outinfo =
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const aco_vp_output_info* outinfo = &ctx->program->info.outinfo;
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ctx->stage.has(SWStage::GS) ? &ctx->program->info.vs.outinfo :
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ctx->stage.has(SWStage::TES) ? &ctx->program->info.tes.outinfo :
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ctx->stage.has(SWStage::MS) ? &ctx->program->info.ms.outinfo :
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&ctx->program->info.vs.outinfo;
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assert(outinfo);
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assert(outinfo);
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ctx->block->kind |= block_kind_export_end;
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ctx->block->kind |= block_kind_export_end;
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@@ -11043,11 +11036,7 @@ static void
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create_primitive_exports(isel_context *ctx, Temp prim_ch1)
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create_primitive_exports(isel_context *ctx, Temp prim_ch1)
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{
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{
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assert(ctx->stage.hw == HWStage::NGG);
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assert(ctx->stage.hw == HWStage::NGG);
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const aco_vp_output_info* outinfo =
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const aco_vp_output_info* outinfo = &ctx->program->info.outinfo;
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ctx->stage.has(SWStage::GS) ? &ctx->program->info.vs.outinfo :
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ctx->stage.has(SWStage::TES) ? &ctx->program->info.tes.outinfo :
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ctx->stage.has(SWStage::MS) ? &ctx->program->info.ms.outinfo :
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&ctx->program->info.vs.outinfo;
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Builder bld(ctx->program, ctx->block);
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Builder bld(ctx->program, ctx->block);
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@@ -247,9 +247,10 @@ get_reg_class(isel_context* ctx, RegType type, unsigned components, unsigned bit
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}
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}
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void
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void
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setup_vs_output_info(isel_context* ctx, nir_shader* nir,
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setup_vs_output_info(isel_context* ctx, nir_shader* nir)
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const aco_vp_output_info* outinfo)
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{
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{
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const aco_vp_output_info* outinfo = &ctx->program->info.outinfo;
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ctx->export_clip_dists = outinfo->export_clip_dists;
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ctx->export_clip_dists = outinfo->export_clip_dists;
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ctx->num_clip_distances = util_bitcount(outinfo->clip_dist_mask);
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ctx->num_clip_distances = util_bitcount(outinfo->clip_dist_mask);
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ctx->num_cull_distances = util_bitcount(outinfo->cull_dist_mask);
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ctx->num_cull_distances = util_bitcount(outinfo->cull_dist_mask);
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@@ -269,7 +270,7 @@ void
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setup_vs_variables(isel_context* ctx, nir_shader* nir)
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setup_vs_variables(isel_context* ctx, nir_shader* nir)
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{
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{
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if (ctx->stage == vertex_vs || ctx->stage == vertex_ngg) {
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if (ctx->stage == vertex_vs || ctx->stage == vertex_ngg) {
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setup_vs_output_info(ctx, nir, &ctx->program->info.vs.outinfo);
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setup_vs_output_info(ctx, nir);
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/* TODO: NGG streamout */
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/* TODO: NGG streamout */
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if (ctx->stage.hw == HWStage::NGG)
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if (ctx->stage.hw == HWStage::NGG)
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@@ -291,7 +292,7 @@ setup_gs_variables(isel_context* ctx, nir_shader* nir)
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ctx->program->config->lds_size =
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ctx->program->config->lds_size =
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ctx->program->info.gfx9_gs_ring_lds_size; /* Already in units of the alloc granularity */
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ctx->program->info.gfx9_gs_ring_lds_size; /* Already in units of the alloc granularity */
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} else if (ctx->stage == vertex_geometry_ngg || ctx->stage == tess_eval_geometry_ngg) {
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} else if (ctx->stage == vertex_geometry_ngg || ctx->stage == tess_eval_geometry_ngg) {
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setup_vs_output_info(ctx, nir, &ctx->program->info.vs.outinfo);
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setup_vs_output_info(ctx, nir);
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ctx->program->config->lds_size =
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ctx->program->config->lds_size =
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DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule);
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DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule);
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@@ -313,7 +314,7 @@ setup_tes_variables(isel_context* ctx, nir_shader* nir)
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ctx->tcs_num_patches = ctx->program->info.num_tess_patches;
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ctx->tcs_num_patches = ctx->program->info.num_tess_patches;
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if (ctx->stage == tess_eval_vs || ctx->stage == tess_eval_ngg) {
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if (ctx->stage == tess_eval_vs || ctx->stage == tess_eval_ngg) {
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setup_vs_output_info(ctx, nir, &ctx->program->info.tes.outinfo);
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setup_vs_output_info(ctx, nir);
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/* TODO: NGG streamout */
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/* TODO: NGG streamout */
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if (ctx->stage.hw == HWStage::NGG)
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if (ctx->stage.hw == HWStage::NGG)
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@@ -331,7 +332,7 @@ setup_tes_variables(isel_context* ctx, nir_shader* nir)
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void
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void
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setup_ms_variables(isel_context* ctx, nir_shader* nir)
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setup_ms_variables(isel_context* ctx, nir_shader* nir)
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{
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{
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setup_vs_output_info(ctx, nir, &ctx->program->info.ms.outinfo);
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setup_vs_output_info(ctx, nir);
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ctx->program->config->lds_size =
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ctx->program->config->lds_size =
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DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule);
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DIV_ROUND_UP(nir->info.shared_size, ctx->program->dev.lds_encoding_granule);
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@@ -920,7 +921,7 @@ setup_isel_context(Program* program, unsigned shader_count, struct nir_shader* c
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unsigned scratch_size = 0;
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unsigned scratch_size = 0;
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if (program->stage == gs_copy_vs) {
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if (program->stage == gs_copy_vs) {
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assert(shader_count == 1);
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assert(shader_count == 1);
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setup_vs_output_info(&ctx, shaders[0], &program->info.vs.outinfo);
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setup_vs_output_info(&ctx, shaders[0]);
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} else {
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} else {
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for (unsigned i = 0; i < shader_count; i++) {
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for (unsigned i = 0; i < shader_count; i++) {
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nir_shader* nir = shaders[i];
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nir_shader* nir = shaders[i];
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@@ -107,8 +107,8 @@ struct aco_shader_info {
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bool has_ngg_early_prim_export;
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bool has_ngg_early_prim_export;
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uint32_t num_tess_patches;
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uint32_t num_tess_patches;
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unsigned workgroup_size;
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unsigned workgroup_size;
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struct {
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struct aco_vp_output_info outinfo;
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struct aco_vp_output_info outinfo;
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struct {
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bool as_es;
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bool as_es;
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bool as_ls;
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bool as_ls;
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bool tcs_in_out_eq;
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bool tcs_in_out_eq;
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@@ -128,7 +128,6 @@ struct aco_shader_info {
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uint32_t num_lds_blocks;
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uint32_t num_lds_blocks;
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} tcs;
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} tcs;
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struct {
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struct {
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struct aco_vp_output_info outinfo;
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bool as_es;
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bool as_es;
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} tes;
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} tes;
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struct {
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struct {
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@@ -142,9 +141,6 @@ struct aco_shader_info {
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struct {
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struct {
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uint8_t subgroup_size;
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uint8_t subgroup_size;
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} cs;
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} cs;
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struct {
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struct aco_vp_output_info outinfo;
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} ms;
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struct aco_streamout_info so;
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struct aco_streamout_info so;
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uint32_t gfx9_gs_ring_lds_size;
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uint32_t gfx9_gs_ring_lds_size;
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@@ -65,7 +65,6 @@ radv_aco_convert_shader_vp_info(struct aco_vp_output_info *aco_info,
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/* don't use export params */
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/* don't use export params */
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}
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}
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#define ASSIGN_OUTINFO(x) radv_aco_convert_shader_vp_info(&aco_info->x.outinfo, &radv->x.outinfo);
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static inline void
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static inline void
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radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
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radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
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const struct radv_shader_info *radv)
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const struct radv_shader_info *radv)
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@@ -76,7 +75,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
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ASSIGN_FIELD(has_ngg_early_prim_export);
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ASSIGN_FIELD(has_ngg_early_prim_export);
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ASSIGN_FIELD(num_tess_patches);
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ASSIGN_FIELD(num_tess_patches);
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ASSIGN_FIELD(workgroup_size);
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ASSIGN_FIELD(workgroup_size);
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ASSIGN_OUTINFO(vs);
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radv_aco_convert_shader_vp_info(&aco_info->outinfo, &radv->outinfo);
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ASSIGN_FIELD(vs.as_es);
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ASSIGN_FIELD(vs.as_es);
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ASSIGN_FIELD(vs.as_ls);
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ASSIGN_FIELD(vs.as_ls);
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ASSIGN_FIELD(vs.tcs_in_out_eq);
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ASSIGN_FIELD(vs.tcs_in_out_eq);
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@@ -90,7 +89,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
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ASSIGN_FIELD_CP(gs.output_streams);
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ASSIGN_FIELD_CP(gs.output_streams);
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ASSIGN_FIELD(gs.vertices_out);
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ASSIGN_FIELD(gs.vertices_out);
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ASSIGN_FIELD(tcs.num_lds_blocks);
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ASSIGN_FIELD(tcs.num_lds_blocks);
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ASSIGN_OUTINFO(tes);
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ASSIGN_FIELD(tes.as_es);
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ASSIGN_FIELD(tes.as_es);
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ASSIGN_FIELD(ps.writes_z);
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ASSIGN_FIELD(ps.writes_z);
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ASSIGN_FIELD(ps.writes_stencil);
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ASSIGN_FIELD(ps.writes_stencil);
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@@ -99,7 +97,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
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ASSIGN_FIELD(ps.num_interp);
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ASSIGN_FIELD(ps.num_interp);
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ASSIGN_FIELD(ps.spi_ps_input);
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ASSIGN_FIELD(ps.spi_ps_input);
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ASSIGN_FIELD(cs.subgroup_size);
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ASSIGN_FIELD(cs.subgroup_size);
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ASSIGN_OUTINFO(ms);
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radv_aco_convert_shader_so_info(aco_info, radv);
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radv_aco_convert_shader_so_info(aco_info, radv);
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aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
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aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
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}
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}
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@@ -174,6 +171,5 @@ radv_aco_convert_opts(struct aco_compiler_options *aco_info,
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#undef ASSIGN_VS_STATE_FIELD_CP
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#undef ASSIGN_VS_STATE_FIELD_CP
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#undef ASSIGN_FIELD
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#undef ASSIGN_FIELD
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#undef ASSIGN_FIELD_CP
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#undef ASSIGN_FIELD_CP
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#undef ASSIGN_OUTINFO
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#endif
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#endif
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@@ -1012,9 +1012,10 @@ radv_llvm_export_vs(struct radv_shader_context *ctx, struct radv_shader_output_v
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}
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}
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static void
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static void
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handle_vs_outputs_post(struct radv_shader_context *ctx, bool export_clip_dists,
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handle_vs_outputs_post(struct radv_shader_context *ctx)
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const struct radv_vs_output_info *outinfo)
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{
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{
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const struct radv_vs_output_info *outinfo = &ctx->shader_info->outinfo;
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const bool export_clip_dists = outinfo->export_clip_dists;
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struct radv_shader_output_values *outputs;
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struct radv_shader_output_values *outputs;
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unsigned noutput = 0;
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unsigned noutput = 0;
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@@ -1157,8 +1158,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi)
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else if (ctx->shader_info->is_ngg)
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else if (ctx->shader_info->is_ngg)
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break; /* Lowered in NIR */
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break; /* Lowered in NIR */
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else
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else
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handle_vs_outputs_post(ctx, ctx->shader_info->vs.outinfo.export_clip_dists,
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handle_vs_outputs_post(ctx);
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&ctx->shader_info->vs.outinfo);
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break;
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break;
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case MESA_SHADER_FRAGMENT:
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case MESA_SHADER_FRAGMENT:
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handle_fs_outputs_post(ctx);
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handle_fs_outputs_post(ctx);
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@@ -1177,8 +1177,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi)
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else if (ctx->shader_info->is_ngg)
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else if (ctx->shader_info->is_ngg)
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break; /* Lowered in NIR */
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break; /* Lowered in NIR */
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else
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else
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handle_vs_outputs_post(ctx, ctx->shader_info->tes.outinfo.export_clip_dists,
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handle_vs_outputs_post(ctx);
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&ctx->shader_info->tes.outinfo);
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break;
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break;
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default:
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default:
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break;
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break;
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@@ -1198,11 +1197,8 @@ static void
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radv_llvm_visit_export_vertex(struct ac_shader_abi *abi)
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radv_llvm_visit_export_vertex(struct ac_shader_abi *abi)
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{
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{
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struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
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struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
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const struct radv_vs_output_info *outinfo = ctx->stage == MESA_SHADER_TESS_EVAL
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? &ctx->shader_info->tes.outinfo
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: &ctx->shader_info->vs.outinfo;
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handle_vs_outputs_post(ctx, outinfo->export_clip_dists, outinfo);
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handle_vs_outputs_post(ctx);
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}
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}
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static void
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static void
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@@ -1692,8 +1688,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
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radv_emit_streamout(ctx, stream);
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radv_emit_streamout(ctx, stream);
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if (stream == 0) {
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if (stream == 0) {
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handle_vs_outputs_post(ctx, ctx->shader_info->vs.outinfo.export_clip_dists,
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handle_vs_outputs_post(ctx);
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&ctx->shader_info->vs.outinfo);
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}
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}
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LLVMBuildBr(ctx->ac.builder, end_bb);
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LLVMBuildBr(ctx->ac.builder, end_bb);
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@@ -2193,7 +2193,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
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* corresponding to the ES thread of the provoking vertex. All
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* corresponding to the ES thread of the provoking vertex. All
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* ES threads load and export PrimitiveID for their thread.
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* ES threads load and export PrimitiveID for their thread.
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*/
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*/
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if (!stages[MESA_SHADER_TESS_CTRL].nir && stages[MESA_SHADER_VERTEX].info.vs.outinfo.export_prim_id)
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if (!stages[MESA_SHADER_TESS_CTRL].nir && stages[MESA_SHADER_VERTEX].info.outinfo.export_prim_id)
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esvert_lds_size = MAX2(esvert_lds_size, 1);
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esvert_lds_size = MAX2(esvert_lds_size, 1);
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}
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}
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@@ -2397,15 +2397,15 @@ get_vs_output_info(const struct radv_graphics_pipeline *pipeline)
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{
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{
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if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
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if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
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if (radv_pipeline_has_ngg(pipeline))
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if (radv_pipeline_has_ngg(pipeline))
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return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
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return &pipeline->base.shaders[MESA_SHADER_GEOMETRY]->info.outinfo;
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else
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else
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return &pipeline->base.gs_copy_shader->info.vs.outinfo;
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return &pipeline->base.gs_copy_shader->info.outinfo;
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else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
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else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
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return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
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return &pipeline->base.shaders[MESA_SHADER_TESS_EVAL]->info.outinfo;
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else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
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else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH))
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return &pipeline->base.shaders[MESA_SHADER_MESH]->info.ms.outinfo;
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return &pipeline->base.shaders[MESA_SHADER_MESH]->info.outinfo;
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else
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else
|
||||||
return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
|
return &pipeline->base.shaders[MESA_SHADER_VERTEX]->info.outinfo;
|
||||||
}
|
}
|
||||||
|
|
||||||
static bool
|
static bool
|
||||||
@@ -3244,7 +3244,7 @@ radv_determine_ngg_settings(struct radv_pipeline *pipeline,
|
|||||||
|
|
||||||
unsigned lds_bytes_if_culling_off = 0;
|
unsigned lds_bytes_if_culling_off = 0;
|
||||||
/* We need LDS space when VS needs to export the primitive ID. */
|
/* We need LDS space when VS needs to export the primitive ID. */
|
||||||
if (es_stage == MESA_SHADER_VERTEX && stages[es_stage].info.vs.outinfo.export_prim_id)
|
if (es_stage == MESA_SHADER_VERTEX && stages[es_stage].info.outinfo.export_prim_id)
|
||||||
lds_bytes_if_culling_off = max_vtx_in * 4u;
|
lds_bytes_if_culling_off = max_vtx_in * 4u;
|
||||||
stages[es_stage].info.num_lds_blocks_when_not_culling =
|
stages[es_stage].info.num_lds_blocks_when_not_culling =
|
||||||
DIV_ROUND_UP(lds_bytes_if_culling_off, pdevice->rad_info.lds_encode_granularity);
|
DIV_ROUND_UP(lds_bytes_if_culling_off, pdevice->rad_info.lds_encode_granularity);
|
||||||
@@ -3255,7 +3255,7 @@ radv_determine_ngg_settings(struct radv_pipeline *pipeline,
|
|||||||
stages[es_stage].info.is_ngg_passthrough = stages[es_stage].info.is_ngg_passthrough &&
|
stages[es_stage].info.is_ngg_passthrough = stages[es_stage].info.is_ngg_passthrough &&
|
||||||
!stages[es_stage].info.has_ngg_culling &&
|
!stages[es_stage].info.has_ngg_culling &&
|
||||||
!(es_stage == MESA_SHADER_VERTEX &&
|
!(es_stage == MESA_SHADER_VERTEX &&
|
||||||
stages[es_stage].info.vs.outinfo.export_prim_id);
|
stages[es_stage].info.outinfo.export_prim_id);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -3359,15 +3359,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
|
|||||||
|
|
||||||
assert(last_vgt_api_stage != MESA_SHADER_NONE);
|
assert(last_vgt_api_stage != MESA_SHADER_NONE);
|
||||||
struct radv_shader_info *pre_ps_info = &stages[last_vgt_api_stage].info;
|
struct radv_shader_info *pre_ps_info = &stages[last_vgt_api_stage].info;
|
||||||
struct radv_vs_output_info *outinfo = NULL;
|
struct radv_vs_output_info *outinfo = &pre_ps_info->outinfo;
|
||||||
if (last_vgt_api_stage == MESA_SHADER_VERTEX ||
|
|
||||||
last_vgt_api_stage == MESA_SHADER_GEOMETRY) {
|
|
||||||
outinfo = &pre_ps_info->vs.outinfo;
|
|
||||||
} else if (last_vgt_api_stage == MESA_SHADER_TESS_EVAL) {
|
|
||||||
outinfo = &pre_ps_info->tes.outinfo;
|
|
||||||
} else if (last_vgt_api_stage == MESA_SHADER_MESH) {
|
|
||||||
outinfo = &pre_ps_info->ms.outinfo;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Add PS input requirements to the output of the pre-PS stage. */
|
/* Add PS input requirements to the output of the pre-PS stage. */
|
||||||
bool ps_prim_id_in = stages[MESA_SHADER_FRAGMENT].info.ps.prim_id_input;
|
bool ps_prim_id_in = stages[MESA_SHADER_FRAGMENT].info.ps.prim_id_input;
|
||||||
@@ -4253,8 +4245,8 @@ radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
|
|||||||
struct radv_device *device = pipeline->device;
|
struct radv_device *device = pipeline->device;
|
||||||
struct radv_shader_info info = {0};
|
struct radv_shader_info info = {0};
|
||||||
|
|
||||||
if (stages[MESA_SHADER_GEOMETRY].info.vs.outinfo.export_clip_dists)
|
if (stages[MESA_SHADER_GEOMETRY].info.outinfo.export_clip_dists)
|
||||||
info.vs.outinfo.export_clip_dists = true;
|
info.outinfo.export_clip_dists = true;
|
||||||
|
|
||||||
radv_nir_shader_info_pass(device, stages[MESA_SHADER_GEOMETRY].nir, pipeline_layout, pipeline_key,
|
radv_nir_shader_info_pass(device, stages[MESA_SHADER_GEOMETRY].nir, pipeline_layout, pipeline_key,
|
||||||
&info);
|
&info);
|
||||||
|
@@ -1284,7 +1284,7 @@ void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_
|
|||||||
num_vertices_per_prim = 2;
|
num_vertices_per_prim = 2;
|
||||||
|
|
||||||
/* Manually mark the primitive ID used, so the shader can repack it. */
|
/* Manually mark the primitive ID used, so the shader can repack it. */
|
||||||
if (info->tes.outinfo.export_prim_id)
|
if (info->outinfo.export_prim_id)
|
||||||
BITSET_SET(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
|
BITSET_SET(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
|
||||||
|
|
||||||
} else if (nir->info.stage == MESA_SHADER_VERTEX) {
|
} else if (nir->info.stage == MESA_SHADER_VERTEX) {
|
||||||
@@ -1313,19 +1313,13 @@ void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_
|
|||||||
|
|
||||||
if (nir->info.stage == MESA_SHADER_VERTEX ||
|
if (nir->info.stage == MESA_SHADER_VERTEX ||
|
||||||
nir->info.stage == MESA_SHADER_TESS_EVAL) {
|
nir->info.stage == MESA_SHADER_TESS_EVAL) {
|
||||||
bool export_prim_id;
|
bool export_prim_id = info->outinfo.export_prim_id;
|
||||||
|
|
||||||
assert(info->is_ngg);
|
assert(info->is_ngg);
|
||||||
|
|
||||||
if (info->has_ngg_culling)
|
if (info->has_ngg_culling)
|
||||||
radv_optimize_nir_algebraic(nir, false);
|
radv_optimize_nir_algebraic(nir, false);
|
||||||
|
|
||||||
if (nir->info.stage == MESA_SHADER_VERTEX) {
|
|
||||||
export_prim_id = info->vs.outinfo.export_prim_id;
|
|
||||||
} else {
|
|
||||||
export_prim_id = info->tes.outinfo.export_prim_id;
|
|
||||||
}
|
|
||||||
|
|
||||||
NIR_PASS_V(nir, ac_nir_lower_ngg_nogs,
|
NIR_PASS_V(nir, ac_nir_lower_ngg_nogs,
|
||||||
device->physical_device->rad_info.family,
|
device->physical_device->rad_info.family,
|
||||||
max_vtx_in, num_vertices_per_prim,
|
max_vtx_in, num_vertices_per_prim,
|
||||||
@@ -1705,7 +1699,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
|
|||||||
|
|
||||||
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
|
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
|
||||||
} else {
|
} else {
|
||||||
bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
|
bool enable_prim_id = info->outinfo.export_prim_id || info->uses_prim_id;
|
||||||
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
||||||
|
|
||||||
config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10);
|
config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10);
|
||||||
@@ -1760,7 +1754,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
|
|||||||
*/
|
*/
|
||||||
if (info->vs.needs_instance_id && pdevice->rad_info.gfx_level >= GFX10) {
|
if (info->vs.needs_instance_id && pdevice->rad_info.gfx_level >= GFX10) {
|
||||||
vgpr_comp_cnt = 3;
|
vgpr_comp_cnt = 3;
|
||||||
} else if (info->vs.outinfo.export_prim_id) {
|
} else if (info->outinfo.export_prim_id) {
|
||||||
vgpr_comp_cnt = 2;
|
vgpr_comp_cnt = 2;
|
||||||
} else if (info->vs.needs_instance_id) {
|
} else if (info->vs.needs_instance_id) {
|
||||||
vgpr_comp_cnt = 1;
|
vgpr_comp_cnt = 1;
|
||||||
@@ -1820,7 +1814,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
|
|||||||
if (es_stage == MESA_SHADER_VERTEX) {
|
if (es_stage == MESA_SHADER_VERTEX) {
|
||||||
es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
|
es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
|
||||||
} else if (es_stage == MESA_SHADER_TESS_EVAL) {
|
} else if (es_stage == MESA_SHADER_TESS_EVAL) {
|
||||||
bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
|
bool enable_prim_id = info->outinfo.export_prim_id || info->uses_prim_id;
|
||||||
es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
||||||
} else if (es_stage == MESA_SHADER_MESH) {
|
} else if (es_stage == MESA_SHADER_MESH) {
|
||||||
es_vgpr_comp_cnt = 0;
|
es_vgpr_comp_cnt = 0;
|
||||||
@@ -1845,7 +1839,7 @@ radv_postprocess_config(const struct radv_device *device, const struct ac_shader
|
|||||||
if (info->uses_invocation_id) {
|
if (info->uses_invocation_id) {
|
||||||
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
|
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
|
||||||
} else if (info->uses_prim_id || (es_stage == MESA_SHADER_VERTEX &&
|
} else if (info->uses_prim_id || (es_stage == MESA_SHADER_VERTEX &&
|
||||||
info->vs.outinfo.export_prim_id)) {
|
info->outinfo.export_prim_id)) {
|
||||||
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
|
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
|
||||||
} else if (need_gs_vtx_offset2) {
|
} else if (need_gs_vtx_offset2) {
|
||||||
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
|
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
|
||||||
|
@@ -253,6 +253,7 @@ struct radv_shader_info {
|
|||||||
uint32_t num_lds_blocks_when_not_culling;
|
uint32_t num_lds_blocks_when_not_culling;
|
||||||
uint32_t num_tess_patches;
|
uint32_t num_tess_patches;
|
||||||
uint32_t esgs_itemsize; /* Only for VS or TES as ES */
|
uint32_t esgs_itemsize; /* Only for VS or TES as ES */
|
||||||
|
struct radv_vs_output_info outinfo;
|
||||||
unsigned workgroup_size;
|
unsigned workgroup_size;
|
||||||
bool force_vrs_per_vertex;
|
bool force_vrs_per_vertex;
|
||||||
struct {
|
struct {
|
||||||
@@ -260,7 +261,6 @@ struct radv_shader_info {
|
|||||||
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
||||||
bool needs_draw_id;
|
bool needs_draw_id;
|
||||||
bool needs_instance_id;
|
bool needs_instance_id;
|
||||||
struct radv_vs_output_info outinfo;
|
|
||||||
bool as_es;
|
bool as_es;
|
||||||
bool as_ls;
|
bool as_ls;
|
||||||
bool tcs_in_out_eq;
|
bool tcs_in_out_eq;
|
||||||
@@ -288,7 +288,6 @@ struct radv_shader_info {
|
|||||||
} gs;
|
} gs;
|
||||||
struct {
|
struct {
|
||||||
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
||||||
struct radv_vs_output_info outinfo;
|
|
||||||
bool as_es;
|
bool as_es;
|
||||||
enum tess_primitive_mode _primitive_mode;
|
enum tess_primitive_mode _primitive_mode;
|
||||||
enum gl_tess_spacing spacing;
|
enum gl_tess_spacing spacing;
|
||||||
@@ -361,7 +360,6 @@ struct radv_shader_info {
|
|||||||
bool tes_reads_tess_factors : 1;
|
bool tes_reads_tess_factors : 1;
|
||||||
} tcs;
|
} tcs;
|
||||||
struct {
|
struct {
|
||||||
struct radv_vs_output_info outinfo;
|
|
||||||
enum shader_prim output_prim;
|
enum shader_prim output_prim;
|
||||||
bool needs_ms_scratch_ring;
|
bool needs_ms_scratch_ring;
|
||||||
bool has_task; /* If mesh shader is used together with a task shader. */
|
bool has_task; /* If mesh shader is used together with a task shader. */
|
||||||
|
@@ -357,23 +357,10 @@ gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
|
|||||||
static struct radv_vs_output_info *
|
static struct radv_vs_output_info *
|
||||||
get_vs_output_info(const nir_shader *nir, struct radv_shader_info *info)
|
get_vs_output_info(const nir_shader *nir, struct radv_shader_info *info)
|
||||||
{
|
{
|
||||||
|
if ((nir->info.stage == MESA_SHADER_VERTEX && !info->vs.as_ls && !info->vs.as_es) ||
|
||||||
switch (nir->info.stage) {
|
(nir->info.stage == MESA_SHADER_TESS_EVAL && !info->tes.as_es) ||
|
||||||
case MESA_SHADER_VERTEX:
|
nir->info.stage == MESA_SHADER_GEOMETRY || nir->info.stage == MESA_SHADER_MESH) {
|
||||||
if (!info->vs.as_ls && !info->vs.as_es)
|
return &info->outinfo;
|
||||||
return &info->vs.outinfo;
|
|
||||||
break;
|
|
||||||
case MESA_SHADER_GEOMETRY:
|
|
||||||
return &info->vs.outinfo;
|
|
||||||
break;
|
|
||||||
case MESA_SHADER_TESS_EVAL:
|
|
||||||
if (!info->tes.as_es)
|
|
||||||
return &info->tes.outinfo;
|
|
||||||
break;
|
|
||||||
case MESA_SHADER_MESH:
|
|
||||||
return &info->ms.outinfo;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return NULL;
|
return NULL;
|
||||||
|
Reference in New Issue
Block a user