radv: drop tcs_out_offsets

Move all calculations to shader generation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

src/amd/vulkan/radv_nir_to_llvm.c

@@ -63,7 +63,6 @@ struct radv_shader_context {
 	LLVMValueRef es2gs_offset;
 
 	LLVMValueRef tcs_offchip_layout;
-	LLVMValueRef tcs_out_offsets;
 	LLVMValueRef oc_lds;
 	LLVMValueRef merged_wave_info;
 	LLVMValueRef tess_factor_offset;
@@ -192,17 +191,37 @@ get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
 static LLVMValueRef
 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
 {
+	assert (ctx->stage == MESA_SHADER_TESS_CTRL);
+	uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+	uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
+	uint32_t output_patch0_offset = input_patch_size;
+	LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
+
+	output_patch0_offset /= 4;
 	return LLVMBuildMul(ctx->ac.builder,
-			    ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
+			    num_patches,
-			    LLVMConstInt(ctx->ac.i32, 4, false), "");
+			    LLVMConstInt(ctx->ac.i32, output_patch0_offset, false), "");
 }
 
 static LLVMValueRef
 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
 {
-	return LLVMBuildMul(ctx->ac.builder,
+	uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
-			    ac_unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
+	uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
-			    LLVMConstInt(ctx->ac.i32, 4, false), "");
+	uint32_t output_patch0_offset = input_patch_size;
+
+	uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+	uint32_t output_vertex_size = num_tcs_outputs * 16;
+	uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
+	LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
+
+	output_patch0_offset /= 4;
+	LLVMValueRef value = LLVMBuildMul(ctx->ac.builder,
+					  num_patches,
+					  LLVMConstInt(ctx->ac.i32, output_patch0_offset, false), "");
+	return LLVMBuildAdd(ctx->ac.builder,
+			    value,
+			    LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size / 4, false), "");
 }
 
 static LLVMValueRef
@@ -474,7 +493,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
 			if (previous_stage == MESA_SHADER_VERTEX)
 				user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
 		}
-		user_sgpr_info->sgpr_count += 2;
+		user_sgpr_info->sgpr_count += 1;
 		break;
 	case MESA_SHADER_TESS_EVAL:
 		user_sgpr_info->sgpr_count += 1;
@@ -772,8 +791,6 @@ static void create_function(struct radv_shader_context *ctx,
 
 			add_arg(&args, ARG_SGPR, ctx->ac.i32,
 				&ctx->tcs_offchip_layout);
-			add_arg(&args, ARG_SGPR, ctx->ac.i32,
-				&ctx->tcs_out_offsets);
 			if (needs_view_index)
 				add_arg(&args, ARG_SGPR, ctx->ac.i32,
 					&ctx->abi.view_index);
@@ -793,8 +810,6 @@ static void create_function(struct radv_shader_context *ctx,
 
 			add_arg(&args, ARG_SGPR, ctx->ac.i32,
 				&ctx->tcs_offchip_layout);
-			add_arg(&args, ARG_SGPR, ctx->ac.i32,
-				&ctx->tcs_out_offsets);
 			if (needs_view_index)
 				add_arg(&args, ARG_SGPR, ctx->ac.i32,
 					&ctx->abi.view_index);
@@ -1003,7 +1018,7 @@ static void create_function(struct radv_shader_context *ctx,
 	case MESA_SHADER_TESS_CTRL:
 		set_vs_specific_input_locs(ctx, stage, has_previous_stage,
 					   previous_stage, &user_sgpr_idx);
-		set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 2);
+		set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
 		if (ctx->abi.view_index)
 			set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
 		break;

src/amd/vulkan/radv_pipeline.c

@@ -62,7 +62,6 @@ struct radv_blend_state {
 
 struct radv_tessellation_state {
 	uint32_t ls_hs_config;
-	uint32_t tcs_out_offsets;
 	uint32_t offchip_layout;
 	unsigned num_patches;
 	unsigned lds_size;
@@ -1314,7 +1313,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 	unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
 	unsigned input_patch_size, output_patch_size, output_patch0_offset;
 	unsigned lds_size, hardware_lds_size;
-	unsigned perpatch_output_offset;
 	unsigned num_patches;
 	struct radv_tessellation_state tess = {0};
 
@@ -1366,7 +1364,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 	}
 
 	output_patch0_offset = input_patch_size * num_patches;
-	perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
 
 	lds_size = output_patch0_offset + output_patch_size * num_patches;
 
@@ -1381,8 +1378,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 
 	tess.lds_size = lds_size;
 
-	tess.tcs_out_offsets = (output_patch0_offset / 16) |
-		((perpatch_output_offset / 16) << 16);
 	tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
 		num_patches;
 
@@ -2612,11 +2607,10 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
 	loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
 	if (loc->sgpr_idx != -1) {
 		uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
-		assert(loc->num_sgprs == 2);
+		assert(loc->num_sgprs == 1);
 		assert(!loc->indirect);
-		radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 2);
+		radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 1);
 		radeon_emit(cs, tess->offchip_layout);
-		radeon_emit(cs, tess->tcs_out_offsets);
 	}
 
 	loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);