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intel/genxml/xe2: Add STATE_SYSTEM_MEM_FENCE_ADDRESS instruction

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Fixes: 86813c60a4 ("mi-builder: add read/write memory fencing support on Gfx20+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32680>
This commit is contained in:
José Roberto de Souza
2024-12-12 09:08:37 -08:00
committed by Marge Bot
parent 9e8824371b
commit edb33b47ab
1 changed files with 9 additions and 0 deletions
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9
src/intel/genxml/gen200.xml
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@@ -1136,6 +1136,15 @@
<field name="UAV Coherency Mode Mask" start="86" end="86" type="uint" />
<field name="Memory allocation for Scratch and Midthread Preemption buffers Mask" start="91" end="91" type="uint" />
</instruction>
<instruction name="STATE_SYSTEM_MEM_FENCE_ADDRESS" bias="2" length="3">
<field name="DWord Length" start="0" end="7" type="uint" default="1" />
<field name="Context Restore Invalid" start="15" end="15" type="bool" default="0" />
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="9" />
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1" />
<field name="Command SubType" start="27" end="28" type="uint" default="0" />
<field name="Command Type" start="29" end="31" type="uint" default="3" />
<field name="System Memory Fence Address" start="44" end="95" type="address" />
</instruction>
<instruction name="XY_BLOCK_COPY_BLT" bias="2" length="22" engine="blitter">
<field name="DWord Length" start="0" end="7" type="uint" default="20" />
<field name="Special Mode of Operation" start="12" end="13" type="uint">